Patent classifications
G06F7/58
Supply authentication via timing challenge response
In an example implementation, a print supply cartridge comprises a microcontroller to receive a timing challenge and enable authentication of the cartridge by providing a challenge response. The challenge response is provided in a challenge response time that falls within an expected time window.
Supply authentication via timing challenge response
In an example implementation, a print supply cartridge comprises a microcontroller to receive a timing challenge and enable authentication of the cartridge by providing a challenge response. The challenge response is provided in a challenge response time that falls within an expected time window.
Data generation device and application execution device
A data processing device according to an aspect of the present invention includes a reception unit, a generation unit, and a transmission unit. The reception unit receives operation requests with respect to an application from an arbitrary number of application execution devices executing the application. The generation unit generates application operation data that includes operation input data for the application and time data indicating the time when the relevant operation input data is applied to the application. The transmission unit transmits the application operation data to the arbitrary number of application execution devices. When an operation request is received from one or more of the arbitrary number of application execution devices, the generation unit generates operation input data on the basis of the relevant operation request.
Data generation device and application execution device
A data processing device according to an aspect of the present invention includes a reception unit, a generation unit, and a transmission unit. The reception unit receives operation requests with respect to an application from an arbitrary number of application execution devices executing the application. The generation unit generates application operation data that includes operation input data for the application and time data indicating the time when the relevant operation input data is applied to the application. The transmission unit transmits the application operation data to the arbitrary number of application execution devices. When an operation request is received from one or more of the arbitrary number of application execution devices, the generation unit generates operation input data on the basis of the relevant operation request.
Semiconductor memory device with mapping factor generating unit for improving reliability
A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.
Controller and operating method thereof
There are provided a controller, an electronic system including the same, and an operating method of the controller and the memory system. The controller includes: a randomizing circuit configured to generate random data having a set number of bits; a masking circuit configured to output select random data by extracting some data according to a number of bits on which a partial encoding operation is to be performed, among the random data; an operating circuit configured to output encoded data and a portion of original data, by performing an operation sequentially on the original data and the select random data; and a cyclic redundancy check circuit configured to generate a cyclic redundancy check value by performing a cyclic redundancy check on the encoded data and the portion of original data, and output partially encoded data including the cyclic redundancy check value, the portion of original data, and the encoded data.
SYSTEMS AND METHODS FOR SECURE RANDOM NUMBER GENERATION
In some implementations, a device may receive, at an operating system, a request for a random number from an application. The device may provide a command to generate an entropy input, based on the request for the random number and through a driver that is isolated from the operating system, to a quantum random number generator that is isolated from one or more processors hosting the operating system. Accordingly, the device may receive the entropy input, from the quantum random number generator, using the driver, and may generate the random number based at least in part on the entropy input. The device may provide the random number to the application.
Random number generator
A random number generator according to one embodiment includes a write circuit, a read circuit, and a signal output circuit. The write circuit inverts magnetization of a magnetic layer of a magnetic tunnel junction element stochastically by supplying current to the magnetic layer. The read circuit reads the magnetization. The signal output circuit generates a random number on the basis of the magnetization read by the read circuit. The random number generator includes a sequence control circuit that controls the write circuit and the read circuit. The sequence control circuit regulates the write circuit to supply the current to the write circuit in a first period, and causes the read circuit to read the magnetization after the first period is finished and then a second period longer than the first period is elapsed.
Memory system, memory controller, and method of operating memory system
Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, when result data obtained by derandomizing data included in a flag area is different from reference data after a random data unit is derandomized based on a seed, it is possible to detect an error occurring in the seed in a process of derandomizing the data and to prevent malfunction of firmware in advance by searching for a target seed and derandomizing the random data unit based on the target seed.
Semiconductor device and semiconductor storage device
A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.