A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

A system for determine presence or quality of an external timing device is provided. The system may include a circuit (e.g., in a field-programmable gate array (FPGA)) having an input, an oscillator, an edge detector, a bit counter, and a calculator element. In some examples, the input may receive an input signal under test. The oscillator may advance a timer at a known rate to facilitate generation of clock samples for the input signal under test. The edge detector may measure edges of the input signal under test based on the clock samples. The circuit may include at least one bit counter to store a count associated with the measured edges for a shorter interval timer period and a longer interval timer period. The calculator element may determine presence or quality of an external timing device based on the count.

An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Systems and/or methods can include a ring based inverter chain that constructs multi-bit flip-flops that store time. The time flip-flops serve as storage units and enable pipeline operations. Single cells used in time series analysis, such as dynamic time warping are rendered by the time-domain circuits. The circuits include time flip-flops, Min, and ABS circuits. A and the matrix can be constructed through the single cells.

A method for preloading an application, a storage medium, and a terminal device are provided. The method includes the following. Current state feature information of the terminal device is acquired, when an application preloading prediction event is detected to be triggered. The current state feature information is input into a plurality of CART prediction models each corresponding to an application in a preset application set, where each of the CART prediction models is generated based on a usage regularity of an associated application corresponding to historical state feature information of the terminal device. A target application to be initiated is predicted according to output results of the CART prediction models, and then the target application is preloaded.

Introduced here is a technique to detect and/or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.

Systems and/or methods can include a ring based inverter chain that constructs multi-bit flip-flops that store time. The time flip-flops serve as storage units and enable pipeline operations. Single cells used in time series analysis, such as dynamic time warping are rendered by the time-domain circuits. The circuits include time flip-flops, Min, and ABS circuits. A and the matrix can be constructed through the single cells.