Computationally efficient mixed precision floating point waveform generation takes advantage of the high-speed generation of waveforms with single-precision floating point numbers while reducing the generally unacceptable loss of precision of pure single-precision floating point to generate any waveform that repeats in 2π. This approaches computes a reference phase in double precision as the modulus of the phase with 2π and then computes offsets to that value in single precision. The double precision reference phase is recomputed as needed depending on how quickly the phase grows and how large a machine epsilon is desired.

Computationally efficient mixed precision floating point waveform generation takes advantage of the high-speed generation of waveforms with single-precision floating point numbers while reducing the generally unacceptable loss of precision of pure single-precision floating point to generate any waveform that repeats in 2π. This approaches computes a reference phase in double precision as the modulus of the phase with 2π and then computes offsets to that value in single precision. The double precision reference phase is recomputed as needed depending on how quickly the phase grows and how large a machine epsilon is desired.

A computer system holds model management information for managing a model for calculating, based on a feature amount of a process pair generated based on a plan history and formed of two processes, a transition probability of the two processes forming the process pair. The computer system comprises: a transition probability calculating unit uses, in a case of receiving input data including a plurality of target processes, the model management information and a feature amount of a process pair formed of a reference target process and a transition destination target process, to thereby calculate a transition probability of the process pair; and a transition probability modifying unit modifies the transition probability of the process pair determined to be unreliable. The transition probability calculating unit generates a new plan by determining the order of execution of the plurality of target processes based on the transition probability of the process pair.

One embodiment can provide a system for estimating a useful life of a load-bearing structure at least partly made of a conductive material. During operation, the system establishes a physics-based damage model for the load-bearing structure, performs a dynamic measurement to obtain at least one conductive property of the load-bearing structure as a function of fatigue cycles, estimates parameters of the physics-based damage model based on the measured conductive property, and estimates the useful life of the load-bearing structure based on the estimated parameters of the physics-based damage model.

A signal conversion circuit and a signal readout circuit are provided. The signal conversion circuit includes: an input switched capacitor, one end receiving an electric signal output by a sensing array, and the other end being coupled to an input end of an operational amplifier; a feedback switched capacitor, one end being coupled to the input end of the operational amplifier, and the other end being coupled to an output end of the operational amplifier; an input switch controlling the input switched capacitor to access the signal conversion circuit or not; and a feedback switch controlling the feedback switched capacitor to access the signal conversion circuit or not, wherein the electric signal output by the sensing array comprises a charge signal, a current signal or a voltage signal, and equivalent impedance of the input switched capacitor and the feedback switched capacitor is related to output characteristics of the sensing array.

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Performing processing using hardware counters in a computer system includes storing, in association with greatest common divisor (GCD) processing of the system, a first variable in a first redundant binary representation and a second variable in a second redundant binary representation. Each such redundant binary representation includes a respective sum term and a respective carry term, and a numerical value being represented by a redundant binary representation is equal to a sum of the sum and carry terms of the redundant binary representation. The process performs redundant arithmetic operations of the GCD processing on the first variable and second variables using hardware counter(s), of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form. The process uses output of the redundant arithmetic operations of the GCD processing to obtain an output GCD of integer inputs to the GCD processing.

The computing device receives a first user input request to modify a structural equation model (SEM) in a graphical user interface. The modification of the SEM includes modifying one or more SEM path diagram elements. The computing device detects whether a first SEM path diagram element is modified responsive to the received first user input request. Based on the detection, the computing device determines whether the modification violates a first set of SEM rules, a second set of SEM rules, or one or more launch conditions prior to initiating execution of the SEM. Based on determining a violation of the SEM rules or the launch conditions or that there was not a violation, the computing device displays a graphical indicator for indicating a fatal error for the SEM modification, a warning error for the SEM modification, or a valid SEM modification.

A computing system and method. The inventive system comprises a user interface for providing user input and output and a RASP controller operationally coupled to the user interface. The RASP controller includes a central processing unit implemented with a microprocessor adapted to program instructions stored in a tangible medium and at least one RASP registers configured to store encoded data. A RASP formatter is operationally coupled to the RASP controller and a RASP memory operationally coupled to the RASP controller and the RASP formatter. A boot memory provides program instructions for execution by the central processing unit whereby computing system effects data storage and retrieval using a primal file structure. In a more specific implementation, an input buffer is included and adapted to store electrical signals representing an arbitrary finite data sequence. The RASP formatter is operationally coupled to the input buffer and includes a converter adapted to convert the sequence into a natural number. The RASP formatter further includes a divider (multiplier?) operationally coupled to the converter and adapted to factor the natural number. The RASP formatter further includes an adder operationally coupled to the divider and adapted to concatenate indices of the factored natural number to form a primary binary string and store the primary binary string in the RASP memory.

An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.