Aspects of the invention include decoding a base address and an offset to generate a first potential memory address and a second potential memory address. A first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array are evaluated. Carry-out bit information is received from a summing operation of the base address and the offset, the operating being performed in parallel to the decoding. The carry-out bit information is used to select either the first cell data or the second cell data.

Aspects of the invention include decoding a base address and an offset to generate a first potential memory address and a second potential memory address. A first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array are evaluated. Carry-out bit information is received from a summing operation of the base address and the offset, the operating being performed in parallel to the decoding. The carry-out bit information is used to select either the first cell data or the second cell data.

Systems and methods for compression of data that exhibits mixed compressibility, such as floating-point data, are provided. As one example, aspects of the present disclosure can be used to compress floating-point data that represents the values of parameters of a machine-learned model. Therefore, aspects of the present disclosure can be used to compress machine-learned models (e.g., for reducing storage requirements associated with the model, reducing the bandwidth expended to transmit the model, etc.).

Systems and methods for compression of data that exhibits mixed compressibility, such as floating-point data, are provided. As one example, aspects of the present disclosure can be used to compress floating-point data that represents the values of parameters of a machine-learned model. Therefore, aspects of the present disclosure can be used to compress machine-learned models (e.g., for reducing storage requirements associated with the model, reducing the bandwidth expended to transmit the model, etc.).

A fixed logic circuit configured to determine one or more of the most significant bits of the multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2.sup.m−1, and m is a positive integer, the fixed logic circuit comprising: division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation:

[00001]$.Math.\frac{2^{i}x}{q}.Math.$ where i is the minimum positive value which satisfies:

[00002]$\frac{2^i}{\left(2^i\mathrm{mod}a\right)}>a*\left(2^m-1\right)+1q=.Math.\frac{2^i}{a}.Math.$ and output logic configured to provide the one or more most significant bits of the result of the division operation as the respective one or more most significant bits of the multiplication operation a*x.

A fixed logic circuit configured to determine one or more of the most significant bits of the multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2.sup.m−1, and m is a positive integer, the fixed logic circuit comprising: division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation:

[00001]$.Math.\frac{2^{i}x}{q}.Math.$ where i is the minimum positive value which satisfies:

[00002]$\frac{2^i}{\left(2^i\mathrm{mod}a\right)}>a*\left(2^m-1\right)+1q=.Math.\frac{2^i}{a}.Math.$ and output logic configured to provide the one or more most significant bits of the result of the division operation as the respective one or more most significant bits of the multiplication operation a*x.

Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A-B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|−|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|−|B|), and the sign of each floating-point number.

Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.