An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

An electronic device includes a coding module that determines whether a parameter of an artificial neural network is an outlier, depending on a value of the parameter and compresses the parameter by truncating a first bit of the parameter when the parameter is a non-outlier and truncating a second bit of the parameter when the parameter is the outlier, and a decoding module that decodes a compressed parameter.

Systems and methods for compression of data that exhibits mixed compressibility, such as floating-point data, are provided. As one example, aspects of the present disclosure can be used to compress floating-point data that represents the values of parameters of a machine-learned model. Therefore, aspects of the present disclosure can be used to compress machine-learned models (e.g., for reducing storage requirements associated with the model, reducing the bandwidth expended to transmit the model, etc.).

Systems and methods for compression of data that exhibits mixed compressibility, such as floating-point data, are provided. As one example, aspects of the present disclosure can be used to compress floating-point data that represents the values of parameters of a machine-learned model. Therefore, aspects of the present disclosure can be used to compress machine-learned models (e.g., for reducing storage requirements associated with the model, reducing the bandwidth expended to transmit the model, etc.).

A secure MSB normalization system includes n distributed processing apparatuses, each including a bit decomposition unit, a logical sum acquisition unit, a shift amount acquisition unit, and a shift unit, the n bit decomposition units decompose a vector [[{right arrow over ( )}a]].sup.P of a (k, n)-secret shared share into bits and obtain a bit representation vector [[{right arrow over ( )}a]].sup.2{circumflex over ( )}L of the vector [[{right arrow over ( )}a]].sup.P, the n logical sum acquisition units obtain a logical sum [[A.sub.i]].sup.2 of all elements for a vector [[{right arrow over ( )}a.sub.i]] at each bit position of the bit representation [[{right arrow over ( )}a]].sup.2{circumflex over ( )}L, the n shift amount acquisition units obtain a share <<ρ>>.sup.p obtained by distributing a shift amount ρ for shifting the most significant bit of a logical sum [[A.sub.0]].sup.2, . . . , [[A.sub.L−1]].sup.2 to a fixed position by (k, n)-replica secret sharing by a modulus p, and the n shift units obtain a vector [[2.sup.ρ{right arrow over ( )}a]].sup.p in which each element of the vector [[{right arrow over ( )}a]].sup.p is shifted left by ρ bits.

A secure MSB normalization system includes n distributed processing apparatuses, each including a bit decomposition unit, a logical sum acquisition unit, a shift amount acquisition unit, and a shift unit, the n bit decomposition units decompose a vector [[{right arrow over ( )}a]].sup.P of a (k, n)-secret shared share into bits and obtain a bit representation vector [[{right arrow over ( )}a]].sup.2{circumflex over ( )}L of the vector [[{right arrow over ( )}a]].sup.P, the n logical sum acquisition units obtain a logical sum [[A.sub.i]].sup.2 of all elements for a vector [[{right arrow over ( )}a.sub.i]] at each bit position of the bit representation [[{right arrow over ( )}a]].sup.2{circumflex over ( )}L, the n shift amount acquisition units obtain a share <<ρ>>.sup.p obtained by distributing a shift amount ρ for shifting the most significant bit of a logical sum [[A.sub.0]].sup.2, . . . , [[A.sub.L−1]].sup.2 to a fixed position by (k, n)-replica secret sharing by a modulus p, and the n shift units obtain a vector [[2.sup.ρ{right arrow over ( )}a]].sup.p in which each element of the vector [[{right arrow over ( )}a]].sup.p is shifted left by ρ bits.

Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.