Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.

Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.

A neural network data processing apparatus includes: an instruction parsing module, configured to split a DMA task into multiple subtasks and acquire configuration information of a data sub-block corresponding to each subtask, where the subtasks are in a one-to-one correspondence with data sub-blocks of transported neural network data; a data reading module, configured to read a first data sub-block according to the configuration information, where the first data sub-block is a data sub-block among data sub-blocks corresponding to multiple subtasks; a data processing module, configured to compress the first data sub-block; a data write-out module, configured to output compressed data resulting from the compression of the first data sub-block.

Methods and apparatuses relating to a hashing accelerator having a frequency scaled message scheduler data path circuit are described. In one embodiment, a hardware accelerator includes a message digest data path circuit comprising a first message digest circuit to output a second state vector, at a first clock rate, based on a first state vector and an output from a first switch, and a second message digest circuit to output a third state vector, at the first clock rate, based on the second state vector and an output from a second switch; a message scheduler data path circuit comprising at least one first message scheduler circuit to output an element into a second message vector, at a second clock rate that is slower than the first clock rate, based on a plurality of elements of a first message vector, and at least one second message scheduler circuit to output an element into a fourth message vector, at the second clock rate that is slower than the first clock rate, based on a plurality of elements of a third message vector; and a controller to switch the first switch at the second clock rate between sourcing a first element of the first message vector and a first element of the third message vector as the output from the first switch, and switch the second switch at the second clock rate between sourcing a second element of the first message vector and a second element of the third message vector as the output from the second switch.

A processing device in a memory sub-system retrieves an input/output (IO) instruction of a plurality of IO instructions from an IO instruction memory in the memory sub-system, the IO instruction comprising a first number of bits. The processing device further generates an IO vector based on the IO instruction, the IO vector comprising a second number of bits, wherein the second number of bits is greater than the first number of bits. In addition, the processing device causes a plurality of IO signals, based on the IO vector, to be driven on a signal communication bus to a memory device in the memory sub-system, wherein the plurality of IO signals comprises a number of signals equal to the second number of bits of the IO vector.

Methods and systems of updating serial attached small computer system interface (SAS)/serial advanced technology attachment (SATA) hard disk drive (HDD) firmware (FW) using a management controller (MC) are provided. The method includes uploading the HDD FW to the MC via the local area network (LAN), breaking the HDD FW into a plurality of chunks, issuing a plurality of write commands and writing the plurality of chunks into the SAS HDD.

A system for monitoring a model in a wind tunnel is provided. The system includes a plurality of sensors attached to a model in a wind tunnel. Each sensor of the plurality of sensors is configured to measure an attribute of the model. The system also includes a computing device in communication with the plurality of sensors. The computing device is programmed to receive a plurality of signals from the plurality of sensors, store a first threshold and a second threshold based on normalized alarm limits associated with at least one of the plurality of sensors, analyze the plurality of signals based, at least in part, on the first threshold and the second threshold, determine that a potentially negative condition is occurring based on the analysis, and alert a user to the potentially negative condition.

A system for monitoring a model in a wind tunnel is provided. The system includes a plurality of sensors attached to a model in a wind tunnel. Each sensor of the plurality of sensors is configured to measure an attribute of the model. The system also includes a computing device in communication with the plurality of sensors. The computing device is programmed to receive a plurality of signals from the plurality of sensors, store a first threshold and a second threshold based on normalized alarm limits associated with at least one of the plurality of sensors, analyze the plurality of signals based, at least in part, on the first threshold and the second threshold, determine that a potentially negative condition is occurring based on the analysis, and alert a user to the potentially negative condition.

Methods and systems of updating serial attached small computer system interface (SAS)/serial advanced technology attachment (SATA) hard disk drive (HDD) firmware (FW) using a management controller (MC) are provided. The method includes uploading the HDD FW to the MC via the local area network (LAN), breaking the HDD FW into a plurality of chunks, issuing a plurality of write commands and writing the plurality of chunks into the SAS HDD.

An electronic device includes a main circuit including a processor, a sub circuit that transits between a first state and a second state, and a power supply circuit that supplies electric power to the main circuit and the sub circuit. An electrical distance between the main circuit and the power supply circuit is shorter than an electrical distance between the main circuit and the sub circuit. When the processor determines to cause the sub circuit to transit from the second state to the first state, the processor increases electric power supplied from the power supply circuit to the sub circuit. The sub circuit transits from the second state to the first state in response to increase of the electric power supplied from the power supply circuit.