A server at a cluster of servers in a data center is described. The server comprises a memory which is part of a distributed memory of the cluster. The server has at least one processor executing transactions and lock-free reads on software objects stored in regions of the distributed memory, the software objects and details of the transactions being replicated in the distributed memory. The server has a network interface card arranged to receive a message indicating a new configuration of the cluster comprising addition, removal or potential failure of at least one of the other servers. The processor is configured to use a recovery process which enables the lock-free reads and committed ones of the transactions to retain the properties of atomicity, consistency, isolation and durability across configuration changes.

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

An apparatus includes a computer server having a chipset and a baseboard management controller, wherein the chipset includes a first serial bus controller, and wherein the baseboard management controller includes a second serial bus controller. The apparatus further includes a serial bus port disposed along an external panel of a server enclosure that houses the computer server, wherein the serial bus port is accessible for connection with a connector of a serial communication cable. Still further, the apparatus includes a switch that selectively connects the serial bus port to either the first serial bus controller or the second serial bus controller, wherein the switch is controlled by an output signal from the baseboard management controller.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

A system for monitoring a model in a wind tunnel is provided. The system includes a plurality of sensors attached to a model in a wind tunnel. Each sensor of the plurality of sensors is configured to measure an attribute of the model. The system also includes a computing device in communication with the plurality of sensors. The computing device is programmed to receive a plurality of signals from the plurality of sensors, store a first threshold and a second threshold based on normalized alarm limits associated with at least one of the plurality of sensors, analyze the plurality of signals based, at least in part, on the first threshold and the second threshold, determine that a potentially negative condition is occurring based on the analysis, and alert a user to the potentially negative condition.

A computing system includes a quantum processor with qubits, a classical memory including a quantum program defining a plurality of instructions in a source language, and a classical processor configured to: (i) receive a circuit of gates representing a quantum program for a variational algorithm in which computation is interleaved with compilation; (ii) identify a plurality of blocks, each block includes a subcircuit of gates, leaving one or more remainder subcircuits of the circuit of gates outside of the plurality of blocks; (iii) pre-compile each block of the plurality of blocks with a pulse generation program to generate a plurality of pre-compiled blocks including control pulses configured to perform the associated block on the quantum processor; and (iv) iteratively execute the quantum program using the pre-compiled blocks as static during runtime and recompiling the one or more remainder subcircuits on the classical processor at each iteration of execution.

A computing core circuit, including: an encoding module, a route sending module, and a control module, wherein the control module is configured to control the encoding module to perform encoding processing on a pulse sequence determined by pulses of at least one neuron in a current computing core to be transmitted, so as to obtain an encoded pulse sequence, and control the route sending module to determine a corresponding route packet according to the encoded pulse sequence, so as to send the route packet. The present disclosure further provides a data processing method, a chip, a board, an electronic device, and a computer-readable storage medium.

A computing core circuit, including: an encoding module, a route sending module, and a control module, wherein the control module is configured to control the encoding module to perform encoding processing on a pulse sequence determined by pulses of at least one neuron in a current computing core to be transmitted, so as to obtain an encoded pulse sequence, and control the route sending module to determine a corresponding route packet according to the encoded pulse sequence, so as to send the route packet. The present disclosure further provides a data processing method, a chip, a board, an electronic device, and a computer-readable storage medium.

A method of synchronizing system state data is provided. The method includes executing a first processor based on initial state data during an update cycle, wherein the initial state data represents a state of the system prior to initiation of the update cycle, detecting changes in state of the system by the first processor using sensors, the changes in state being added to a record of modified state data until a predefined progress position within the update cycle, designating the modified state data as next state data, based on reaching the predefined progress position within the update cycle, and transitioning from execution of the first processor based on the initial state data to execution of the first processor based on the next state data, based on completion of the update cycle.

A system for monitoring a model in a wind tunnel is provided. The system includes a plurality of sensors attached to a model in a wind tunnel. Each sensor of the plurality of sensors is configured to measure an attribute of the model. The system also includes a computing device in communication with the plurality of sensors. The computing device is programmed to receive a plurality of signals from the plurality of sensors, store a first threshold and a second threshold based on normalized alarm limits associated with at least one of the plurality of sensors, analyze the plurality of signals based, at least in part, on the first threshold and the second threshold, determine that a potentially negative condition is occurring based on the analysis, and alert a user to the potentially negative condition.