A method is used in managing data relocation in storage systems. Data access activity information is gathered for a set of slices of a storage tier in a data storage system for migrating the set of slices from the storage tier to another storage tier. The data storage system includes a first storage tier and a second storage tier configured such that performance characteristics associated with the first storage tier is superior to the second storage tier. Based on a pattern indicated by the data access activity information, a temperature for the set of slices is determined by applying a predictive analysis technique. Based on the determination, relocation of data is effected in the storage system.

A measurement system includes a receiver configured to receive a measurement signal indicative of a parameter of a measured object. The measurement system also includes a processor configured to iteratively filter the measurement signal using a threshold value. The processor is also configured to adjust the threshold value for each iteration of filtration and determine a signal-to-noise ratio for each iteration of filtration. The processor is also configured to set a filter threshold value to the threshold value for the iteration based on the signal-to-noise ratio.

An information handling system detects an initial insertion of an alternating current (AC) adapter, and determines an identifier associated with the AC adapter. The system may also determine a parameter for attenuating noise generated by the AC adapter based on the identifier, and attenuate the noise generated by the AC adapter by applying the parameter.

A method and apparatus with cosmic ray fault protection is included. A method includes obtaining cosmic ray information indicating at least one cosmic ray event, determining a soft error mitigation policy based on the cosmic ray information, accessing the soft error mitigation policy by a device, and based on the soft error mitigation policy, performing, by the device, a mitigation action that mitigates for soft errors related to the cosmic ray event.

A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

In certain embodiments, a system includes first and second resistive components and a touch sensor controller. The first component is positioned on a first sense line connected to an in-cell touch sensor. The first resistive component is set to a value modifying an RC time constant of a first electrode of the touch sensor. The second resistive component is positioned on a second sense line connected to the in-cell touch sensor. The second component is set to a value modifying an RC time constant of a second electrode of the touch sensor. The value of the modified RC time constant of the first electrode is within 100% of the value of the modified RC time constant of the second electrode. The controller receives signals from the first and second sense lines, such that the first and second resistive components are between the controller and the first and second electrodes, respectively.

Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

This disclosure generally provides an input device that includes a matrix sensor that includes a plurality of sensor electrodes arranged in rows on a common surface or plane. The input device may include a plurality of sensor modules coupled to the sensor electrodes that measure capacitive sensing signals corresponding to the electrodes. Instead of measuring sensor electrodes that are in the same column, the embodiments herein simultaneously measure capacitive sensing signals on at least two sensor electrodes that are in the same row. In one example, the sensor electrodes in the row being measured are spaced the same distance from a side of a substrate coupling the electrodes to the sensor modules and may have approximately the same electrical time constant.

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs.