Patent classifications
G06F11/07
Maintenance command interfaces for a memory system
Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.
Semiconductor device and method for protecting bus
The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
Systems and methods for routing remote application data
Described embodiments provide for routing remote application data. A device can receive a request to access an application. The application can be provided by data centers and accessible via service providers. The device can select a data center from the plurality of data centers and a service provider based at least on a metric indicative of a connection between the data center and the service provider. The device can query a database including one or more connection metrics using the application identified in the request and a location of a router transmitting the request. The device can determine the location of the router based on an internet protocol (IP) address of a client communicably coupled to the router. The device can transmit a response to the request identifying the selected data center and the selected service provider.
Reporting control information errors
Methods, systems, and devices for reporting control information errors are described. A state of a memory array may be monitored during operation. After detecting an error (e.g., in received control information), the memory device may enter a first state (e.g., a locked state) and may indicate to a host device that an error was detected, the state of the memory array before the error was detected, and/or at least a portion of a control signal carrying the received control information. The host device may diagnose a cause of the error based on receiving the indication of the error and/or the copy of the control signal. After identifying and/or resolving the cause of the error, the host device may transmit one or more commands (e.g., unlocking the memory device and returning the memory array to the original state) based on receiving the original state from the memory device.
Memory error detection
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
Computing system and method for automated program error repair
This application relates to a computing system and method for an automated program error repair. In one aspect, the computing system includes a storage, a preprocessing processor, and an automated error repair processor. The storage stores a program code. The preprocessing processor acquires the program code from the storage and preprocesses the program code. Preprocessing includes tokenizing the program code with tokens, converting the tokens into vectors, and adding location information for the tokens. The automated error repair processor receives the preprocessed program code as an input from the preprocessing processor, detects an error in the preprocessed program code, corrects the detected error, and outputs the error-corrected program code. Detecting and correcting the error are performed based on a deep learning result and the location information for the tokens.
Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments
A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.
Processing rest API requests based on resource usage satisfying predetermined limits
A request manager analyzes API calls from a client to a host application for state and performance information. If current utilization of host application processing or memory footprint resources exceed predetermined levels, then the incoming API call is not forwarded to the application. If current utilization of the host application processing and memory resources do not exceed the predetermined levels, then the request manager quantifies the processing or memory resources required to report the requested information and determines whether projected utilization of the host application processing or memory resources inclusive of the resources required to report the requested information exceed predetermined levels. If the predetermined levels are not exceeded, then the request manager forwards the API call to the application for processing.
Subsystem for configuration, security, and management of an adaptive system
An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
Bit error rate based dynamic program step characteristic adjustment
A BER corresponding to a group of memory cells programmed via a programing signal having one or more program step characteristics is determined. The determined BER and a target BER is compared. In response to the determined BER being different than the target BER, one or more program step characteristics are adjusted to adjust the determined BER to the target BER.