A system and method for providing status information during a power-on self-test routine. The system includes a basic input output system operable to execute the power-on self-test routine and output the status of the power-on self-test routine. The system includes an externally visible indicator such as a server chassis identify LED. A controller is coupled to the basic input output system and the externally visible indicator. The controller is operable to receive the status from the basic input output system, and to control the externally visible indicator in response to the status received from the basic input output system.

Provided are a method and an apparatus for testing AI chip computing performance, and a non-transitory computer-readable storage medium. The method includes: forming computing performance result data of a to-be-tested AI chip according to a plurality of items of simulation data formed in a development process of the to-be-tested AI chip; acquiring a function instruction set matched with a to-be-tested service function, wherein the function instruction set is composed of a plurality of instructions in a standard instruction set matched with the to-be-tested AI chip; and predicting computing time required by the to-be-tested AI chip to execute the to-be-tested service function according to the function instruction set and the computing performance result data.

A system for configuring an information handling system into a minimum configuration mode. If an information handling system hangs, embodiments may communicate with a remote access controller to set a configuration flag corresponding to a minimum configuration mode. When the information handling system starts a POST process, the BIOS checks the configuration flag. If the flag is set, the BIOS initializes a single DIMM and bypasses any PCIe slot driver initializations and any non-essential services to allow the information handling system to complete the boot process. The information handling system may boot to a UEFI code to allow a user to diagnose a problem or boot to a BIOS setup code to allow the user to enable additional DIMMs, PCIe slots and turn on non-essential services.

A secure boot policy may be stored in the information handling system and used to create a trusted relationship with a CPU, including a neutral CPU that has not been fused with an OEM key. The secure boot policy may be a data blob including platform-specific identification information (e.g., one or more of flash memory unique ID, motherboard ePPID), a boot policy (e.g., specifying to enable or disable neutral CPU fusing), and a signature. The secure boot policy may be stored in a one-time-programmable (OTP) storage of the information handling system, such as an OTP region in the serial peripheral interface (SPI) flash memory part storing the basic input/output system (BIOS). The BIOS may verify the secure boot policy using a public key and check if the boot policy is bound to current BIOS flash part and/or system configuration, and then apply the boot policy if the verification is passed.

This verification processing device is provided with: an inspection unit that performs model inspection on an inspection target model including a plurality of elements; a selection unit that selects at least one of the plurality of elements included in a counterexample outputted as a result of the model inspection; and an exclusion history generation unit that generates exclusion history information indicating an exclusion frequency for each of the plurality of elements. The inspection unit further performs another model inspection on the inspection target model obtained by excluding the selected element. When another counterexample has been outputted as a result of another model inspection, the exclusion history generation unit increases the exclusion frequency of the selected element and updates the exclusion history information. The selection unit selects an element that is high in the exclusion frequency, on the basis of the exclusion history information.

In different example embodiments, a system-on-chip is provided. The system-on-chip can have a control circuit with a plurality of control circuit areas, wherein the control circuit is configured to control a device, a security circuit which has a separately secured key memory and a hardware accelerator for cryptographic operations, wherein the security circuit is configured to electively enable either a read-only access or a read and write access to at least one of the control circuit areas, wherein the security circuit is furthermore configured to provide a communication path by means of the key memory and the hardware accelerator for the secured communication with a diagnostic system disposed outside the security circuit, to make the selection between the read access and the read and write access to the at least one selected area of the control circuit depending on a certificate supplied to the security circuit and authenticated by means of information stored in the key memory, and to execute the read access or the read and write access.

A method of testing a distribution center bus system having one or more of the following features: (a) opening a reserve bus breaker between a reserve bus UPS and a reserve bus, (b) initiating a self-test mode at the reserve bus UPS, (c) routing current through the reserve bus UPS, the reserve bus, a reserve bus static bypass circuit back to the reserve bus UPS, (d) testing the reserve bus to detect heat, determine any significant current loss, or identify other attributes suggesting failure, (e) identifying if a primary bus static transfer switch has tripped over to the reserve bus, and (f) terminating the self-test at the reserve bus UPS if the primary bus static transfer switch has tripped.

An electronic evaluation device and method thereof for optimizing an operation of computer-controlled metric appliances in a network. The method includes determining whether a fault associated with computer-controlled metric appliance is valid based on a feedback received in real time from a validation entity and updating pre-defined programmable instructions assigned to the computer-controlled metric appliance in response to determining that the fault is invalid. The predefined programmable instructions are used to determine whether the computer-executable metric is achieved or not. The method includes applying a machine learning model on the plurality of parameters and the computer-executable goal to determine a computer-executable task list to be assigned to the computer-controlled metric appliance in order to achieve the computer-executable goal.

Devices, systems, and methods for providing an engine control system configured with a two-part test equipment monitor where at least one part is selectively removable are disclosed. An engine control system for an aircraft includes an electronic control unit (ECU). The ECU is configured to implement a production support equipment module and a selectively removable test support equipment module. The production support equipment module enables restricted data monitoring of the engine control system. The test support equipment module enables a comprehensive interface with the engine control system when installed with the ECU.

A central processing unit includes a core, a state memory, a plurality of bus contacts, a data generation unit, and a bus interface unit. The state memory stores a state, the bus interface unit is coupled to the core and the state memory, and the bus interface unit selectively couples the core to the plurality of bus contacts or the data generation unit according to the state.