In a general aspect, a method can include: executing an operation of a program that loads an arbitrarily chosen value of an initial data item of a series of ordered data; executing a series of calculation operations distributed in the program, that calculate a current data item based on a preceding data item; performing a final calculation operation of the series of operations that calculates a final data item of the data series; and executing an operation of the program that detects a program execution error by comparing the current data item of the data series with an expected value of the current data item or the final data item, the final data item having an expected value that is independent of the number of data items in the data series and is calculated based on the current data item of the data series and a final compensation data item.

Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.

Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.

A failure detection circuit for a motor vehicle electronic computer, including: a main microcontroller having at least two microcontroller cores configured to execute the same instructions in parallel, and at least one first software module providing a critical function of a motor vehicle. The first software module includes a predetermined input point and a predetermined output point a supervision microcontroller and a synchronous communication interface for coupling the main microcontroller and the supervision microcontroller so as to enable mutual supervision. The detection circuit makes it possible to detect systematic and random failures.

A failure detection circuit for a motor vehicle electronic computer, including: a main microcontroller having at least two microcontroller cores configured to execute the same instructions in parallel, and at least one first software module providing a critical function of a motor vehicle. The first software module includes a predetermined input point and a predetermined output point a supervision microcontroller and a synchronous communication interface for coupling the main microcontroller and the supervision microcontroller so as to enable mutual supervision. The detection circuit makes it possible to detect systematic and random failures.

A data transmission method of transmitting data of log information recorded in log data of a manufacturing apparatus to an external device includes: storing correspondence information between information of a first identifier and information of a second identifier, the first identifier being an identifier used to identify a thing about a process performed by the manufacturing apparatus and being shared by the manufacturing apparatus and the external device, the second identifier being an identifier used to identify a thing about a process performed by the manufacturing apparatus and being used by the manufacturing apparatus; and obtaining, based on the correspondence information, information of the first identifier corresponding to information of the second identifier recorded in log information, and transmitting data of the log information to which the obtained information of the first identifier has been added. The storing and the obtaining are executed by an information processing device.

A data transmission method of transmitting data of log information recorded in log data of a manufacturing apparatus to an external device includes: storing correspondence information between information of a first identifier and information of a second identifier, the first identifier being an identifier used to identify a thing about a process performed by the manufacturing apparatus and being shared by the manufacturing apparatus and the external device, the second identifier being an identifier used to identify a thing about a process performed by the manufacturing apparatus and being used by the manufacturing apparatus; and obtaining, based on the correspondence information, information of the first identifier corresponding to information of the second identifier recorded in log information, and transmitting data of the log information to which the obtained information of the first identifier has been added. The storing and the obtaining are executed by an information processing device.

A method is described that includes receiving an application and generating a representation of the application that describes specific states of the application and specific state transitions of the application. The method further includes identifying a region of interest of the application based on rules and observations of the application's execution. The method further includes determining specific stimuli that will cause one or more state transitions within the application to reach the region of interest. The method further includes enabling one or more monitors within the application's run time environment and applying the stimuli. The method further includes generating monitoring information from the one or more monitors. The method further includes applying rules to the monitoring information to determine a next set of stimuli to be applied to the application in pursuit of determining whether the region of interest corresponds to improperly behaving code.

Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.

Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.