Examples include an example computing system comprising a first storage to store executable code, wherein the executable code comprises a plurality of instructions, a second storage to store a first parameter of the executable code, a processing unit to execute each of the instructions of the code, and a monitoring component to, upon execution of each of the instructions of the code by the processing unit, update a second parameter of the code based on that instruction, wherein the monitoring component is to compare the first parameter and the second parameter, and to control execution of further executable code by the processing unit based on the comparison.

One or more techniques and/or computing devices are provided for implementing synchronous replication. For example, a synchronous replication relationship may be established between a first storage controller hosting local storage and a second storage controller hosting remote storage (e.g., replication may be specified at a file, logical unit number (LUN), or any other level of granularity). Data operations and offloaded operations may be implemented in parallel upon the local storage and the remote storage. Error handling operations may be implemented upon the local storage and implement in parallel as a best effort on the remote storage, and a reconciliation may be performed to identify any data divergence from the best effort parallel implementation. Storage area network (SAN) operations may be implemented upon the local storage, and upon local completion may be remotely implemented upon the remote storage.

Exposing a memory cell value during trace replay prior to an execution time at which the memory cell value was recorded into a trace. A computer system identifies a trace fragment that records an uninterrupted consecutive execution of executable instructions. Based on performing an intra-fragment analysis of the trace fragment, the computer system determines that a memory cell value recorded into the trace fragment is compatible with memory access(es) to the memory cell that occurred during recording, prior to an event that caused the memory cell value to be recorded. The computer system determines that the memory cell value can be exposed, during trace replay, at a first execution time that is prior to a second execution time corresponding to the event that caused the value to be recorded, and generates output data indicating that the memory cell value can be exposed at the first execution time during trace replay.

Trap sub-portions of computer-readable instructions and related systems, methods, and devices are disclosed. A processing circuit includes a processing core including a program counter to cycle through addresses and a data storage device including computer-readable instructions stored thereon. Sub-portions of the computer-readable correspond to subroutines. Locations of the sub-portions within the data storage device are associated with the addresses. A first sub-portion at a first location within the data storage device is indicated by a first address. First trap sub-portions at first trap locations are indicated by first trap addresses. The first trap addresses are different from the first address by only a single bit. The first trap sub-portions instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves.

Trap sub-portions of computer-readable instructions and related systems, methods, and devices are disclosed. A processing circuit includes a processing core including a program counter to cycle through addresses and a data storage device including computer-readable instructions stored thereon. Sub-portions of the computer-readable correspond to subroutines. Locations of the sub-portions within the data storage device are associated with the addresses. A first sub-portion at a first location within the data storage device is indicated by a first address. First trap sub-portions at first trap locations are indicated by first trap addresses. The first trap addresses are different from the first address by only a single bit. The first trap sub-portions instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves.

The present application relates to a kernel debugging system and method. The kernel debugging system includes: a user interface module, the user interface module being configured to edit program codes and output an execution result of the program codes; a compilation module, the compilation module being configured to compile the program codes into object files; and a Kwasm engine, the Kwasm engine being directly installed in a system kernel of an operating system, and being configured to interpret and execute the object files in a kernel mode, so as to obtain the execution result of the program codes. On the basis of the kernel debugging system, a user can write program codes like writing a common application program, namely, the program codes can be run and executed in a system kernel without paying attention to details of the system kernel.

The present application relates to a kernel debugging system and method. The kernel debugging system includes: a user interface module, the user interface module being configured to edit program codes and output an execution result of the program codes; a compilation module, the compilation module being configured to compile the program codes into object files; and a Kwasm engine, the Kwasm engine being directly installed in a system kernel of an operating system, and being configured to interpret and execute the object files in a kernel mode, so as to obtain the execution result of the program codes. On the basis of the kernel debugging system, a user can write program codes like writing a common application program, namely, the program codes can be run and executed in a system kernel without paying attention to details of the system kernel.

Exposing a memory cell value during trace replay prior to an execution time at which the memory cell value was recorded into a trace. A computer system identifies a trace fragment that records an uninterrupted consecutive execution of executable instructions. Based on performing an intra-fragment analysis of the trace fragment, the computer system determines that a memory cell value recorded into the trace fragment is compatible with memory access(es) to the memory cell that occurred during recording, prior to an event that caused the memory cell value to be recorded. The computer system determines that the memory cell value can be exposed, during trace replay, at a first execution time that is prior to a second execution time corresponding to the event that caused the value to be recorded, and generates output data indicating that the memory cell value can be exposed at the first execution time during trace replay.

Trap sub-portions of computer-readable instructions and related systems, methods, and devices are disclosed. A processing circuit includes a processing core including a program counter to cycle through addresses and a data storage device including computer-readable instructions stored thereon. Sub-portions of the computer-readable correspond to subroutines. Locations of the sub-portions within the data storage device are associated with the addresses. A first sub-portion at a first location within the data storage device is indicated by a first address. First trap sub-portions at first trap locations are indicated by first trap addresses. The first trap addresses are different from the first address by only a single bit. The first trap sub-portions instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves.

During an execution of a first executable entity, a computer system determines that a target chunk of executable instructions is to be recorded during the execution. Prior to executing the target chunk of executable instructions, the computer system identifies one or more input(s) of the target chunk of executable instructions, and adjusts a page table entry to cause a page fault based on an access by a second executable entity to a first memory page that corresponds to an identified input, and/or an access by the first executable entity to a second memory page that does not correspond to any identified input. Based on detecting an occurrence of a page fault during an execution of the target chunk of executable instructions, the computer system detects that there an interference with an identified input by the second executable entity and/or an incompleteness of the identified inputs.