A compute instance is instrumented to detect certain kernel memory allocation functions, in particular functions that allocate heap memory and/or make allocated memory executable. Dynamic shell code exploits can then be detected when code executing from heap memory allocates additional heap memory and makes that additional heap memory executable.

Memory access control circuitry controls handling of a memory access request based on at least one memory access control attribute associated with a region of address space including the target address. The memory access control circuitry comprises: lookup circuitry comprising a plurality of sets of comparison circuitry, each set of comparison circuitry to detect, based on at least one address-region-indicating parameter associated with a corresponding region of address space, whether the target address is within the corresponding region of address space; region mismatch prediction circuitry to provide a region mismatch prediction indicative of which of the sets of comparison circuitry is predicted to detect a region mismatch condition; and comparison disabling circuitry to disable at least one of the sets of comparison circuitry that is predicted by the region mismatch prediction circuitry to detect the region mismatch condition for the target address.

Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.

Systems and methods are described for enabling garbage collection on data storage systems. Traditional garbage collection often attempts to track use of data items on an individual level, deleting each item when it is no longer used. In distributed systems, tracking use on an individual level is difficult, and may require centralized knowledge across the system with respect to individual data items. Provided herein is a “coarse-grained” garbage collection mechanism, which divides objects into logical groups referred to as “roots.” Each root has a life cycle. While active, new data can be stored in a root. While inactive, use of data within a root can cause that date to be copied to a different, active root. When the system detects that data hasn't been used in an inactive root for a threshold period, the root can be considered “dead” and data within the root may be deleted.

Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.

Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an instruction-based power model executed by the computer hardware, a based on the pipeline snapshot data. The plurality of estimates of power consumption are calculated using the instruction-based power model based on the plurality of snapshots over the plurality of clock cycles.

A mapping table management method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a read command from a host system, wherein the read command indicates reading a first data stored in at least one first logical address; and searching whether a relation management information reflects that a first group static mapping table recording the first logical address is related to a dynamic mapping table. In response to a search result reflecting that the first group static mapping table is related to the dynamic mapping table, the dynamic mapping table is searched to obtain a first physical address mapped by the first logical address. And if not related, the first group static mapping table among group static mapping tables is searched to obtain a second physical address mapped by the first logical address.

Systems and methods are disclosed for the intelligent scheduling of garbage collection operations on a solid state memory. In certain embodiments, a method may comprise initiating a garbage collection process for a solid state memory (SSM) having a multiple die architecture, determining an order of die access for the garbage collection process based on an activity table indicating a use of one or more die in the multiple die architecture, and performing the garbage collection process based on the determined order of die access. Garbage collection reads may be directed to idle die to avoid conflicts with die busy performing other operations, thereby improving system performance.

Upon receiving a request to hibernate a hypervisor of a virtualization system running on a first computer, acts are carried out to capture a state of the hypervisor, where the state of the hypervisor comprises hypervisor logical resource parameters and an execution state of the hypervisor. After hibernating the hypervisor by quiescing the hypervisor and storing the state of the hypervisor into a data structure, the data structure is moved to a different location. At a later moment in time, the data structure is loaded onto a second computing machine and restored. The restore operation restores the hypervisor and all of its state, including all of the virtual machines of the hypervisor as well as all of the virtual disks and other virtual devices of the virtual machines. Differences between the first computing machine and the second computing machine are reconciled before execution of the hypervisor on the second machine.