Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

A storage network processing system includes a processor, a network interface and memory that stores operational instructions. The operation instructions enable the processor to receive a data object for storage and dispersed error encode the data object in accordance with dispersed error encoding parameters to produce a plurality of encoded data slices. The operation instructions further enable the processor to generate to determine a plurality of site slice sets from the plurality of encoded data slices, where each site slice set of the plurality of site slice sets includes a number of unique encoded data slices of the plurality of encoded data slices that is greater than or equal to a site write threshold value. The operation instructions further enable the processor to a designate one of a plurality of storage sites for each of the plurality of site slice sets and transmit each of the plurality of site slice sets to a corresponding designated one of the plurality of storage sites via the network.

Systems, devices, apparatuses, components, methods, and techniques for predicting user and media-playback device states are provided. Systems, devices, apparatuses, components, methods, and techniques for representing cached, user-selected, and streaming content are also provided.

An apparatus has tag checking circuitry responsive to a target address to: identify a guard tag stored in a memory system in association with a block of one or more memory locations, the block containing a target memory location identified by the target address, perform a tag check based on the guard tag and an address tag associated with the target address, and in response to detecting a mismatch in the tag check, perform an error response action. The apparatus also has tag mapping storage circuitry to store mapping information indicative of a mapping between guard tag values and corresponding address tag values. The tag checking circuitry remaps at least one of the guard tag and the address tag based on the mapping information stored by the tag mapping storage circuitry to generate a remapped tag for use in the tag check.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

Systems and methods authenticate storage devices. In one implementation, a computer-implemented method is provided for authenticating a storage device. According to the method, a manifest that identifies a destination is receive. A transfer station reads a digital signature from the storage device. The digital signature is validated and, based on the validation of the digital signature, a transfer of one or more files from the storage device via the transfer station is authorized to the destination identified in the manifest.

The present disclosure discloses a control device of data storage system, including a host interface, a peer interface, a storage unit interface, a processor and a local data management module. The host interface is connected and communicated with a storage server for data interaction with the storage server. The peer interface is configured for data communication connection with a storage unit of an adjacent control device in the data storage system. The storage unit interface is configured to connect a storage unit. The local data management module is configured for local data management of the data in the storage unit according to the data management instruction via the processor. The host interface is configured to send result data of local data management to the storage server.

An apparatus to facilitate data cache security is disclosed. The apparatus includes a cache memory to store data; and prefetch hardware to pre-fetch data to be stored in the cache memory, including a cache set monitor hardware to determine critical cache addresses to monitor to determine processes that retrieve data from the cache memory; and pattern monitor hardware to monitor cache access patterns to the critical cache addresses to detect potential side-channel cache attacks on the cache memory by an attacker process.

An apparatus to facilitate data cache security is disclosed. The apparatus includes a cache memory to store data; and prefetch hardware to pre-fetch data to be stored in the cache memory, including a cache set monitor hardware to determine critical cache addresses to monitor to determine processes that retrieve data from the cache memory; and pattern monitor hardware to monitor cache access patterns to the critical cache addresses to detect potential side-channel cache attacks on the cache memory by an attacker process.

A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.