Systems and processes for intelligent device identification are provided. In one example process, audio input may be sampled with a microphone at each of two or more of the plurality of electronic devices. A first electronic device of the plurality of electronic devices for determining a task associated with sampled audio input may be identified. The process may determine the task based on the sampled audio input with the first electronic device and identify identifying a second electronic device of the plurality of electronic devices for performing the task. The task be performed with the second electronic device. The second electronic device is not the first electronic device in some examples.

Systems and processes for intelligent device identification are provided. In one example process, audio input may be sampled with a microphone at each of two or more of the plurality of electronic devices. A first electronic device of the plurality of electronic devices for determining a task associated with sampled audio input may be identified. The process may determine the task based on the sampled audio input with the first electronic device and identify identifying a second electronic device of the plurality of electronic devices for performing the task. The task be performed with the second electronic device. The second electronic device is not the first electronic device in some examples.

A device includes a hardware data processing node configured to execute a respective task, and a hardware thread scheduler including a hardware task scheduler. The hardware task scheduler is coupled to the hardware data processing node and has a producer socket, a consumer socket, and a spare socket. The spare socket is configured to provide data control signals also provided by a first socket of the producer and consumer sockets responsive to a memory-mapped register being a first value. The spare socket is configured to provide data control signals also provided by a second socket of the producer and consumer sockets responsive to the memory-mapped register being a second value.

A medical device comprises a control system, processing modules, and a wire bundle connecting the control system to the processing modules, the wire bundle comprising control lines and data lines. Each processing module is coupled to a respective set of sensors arranged to interface with a biological tissue site, the sensors being configured to capture analog physiological signals generated from the biological tissue site. The control system is configured to generate a control signal on the control lines to initiate a data collection cycle by the processing modules. In response to the control signal, each processing module is configured to perform a respective data collection process which comprises (i) capturing and processing an analog physiological signal on each enabled sensor to generate a data sample for each analog physiological signal captured on each enabled sensor, and (ii) outputting data samples to the control system on the data lines.

A medical device comprises a control system, processing modules, and a wire bundle connecting the control system to the processing modules, the wire bundle comprising control lines and data lines. Each processing module is coupled to a respective set of sensors arranged to interface with a biological tissue site, the sensors being configured to capture analog physiological signals generated from the biological tissue site. The control system is configured to generate a control signal on the control lines to initiate a data collection cycle by the processing modules. In response to the control signal, each processing module is configured to perform a respective data collection process which comprises (i) capturing and processing an analog physiological signal on each enabled sensor to generate a data sample for each analog physiological signal captured on each enabled sensor, and (ii) outputting data samples to the control system on the data lines.

Methods and systems are provided for performing lossy dropping and ECN marking in a flow-based network. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform per-flow packet dropping and ECN marking.

A data transmission device includes a data identification portion, an error determination portion and an output control portion. The data identification portion, based on a detected position of a predetermined bit string in a bit string received via a serial transmission path, identifies a plurality of parallel data corresponding to one line of image data included in the bit string. The error determination portion determines whether or not there is an error in each of the parallel data identified by the data identification portion. The output control portion, in a case where it is determined that none of the plurality of parallel data has an error, outputs the plurality of parallel data and stores the plurality of parallel data in a storage portion, and in a case where it is not determined that there is no error, outputs the plurality of parallel data stored in the storage portion.

A data transmission device includes a data identification portion, an error determination portion and an output control portion. The data identification portion, based on a detected position of a predetermined bit string in a bit string received via a serial transmission path, identifies a plurality of parallel data corresponding to one line of image data included in the bit string. The error determination portion determines whether or not there is an error in each of the parallel data identified by the data identification portion. The output control portion, in a case where it is determined that none of the plurality of parallel data has an error, outputs the plurality of parallel data and stores the plurality of parallel data in a storage portion, and in a case where it is not determined that there is no error, outputs the plurality of parallel data stored in the storage portion.

A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.