Configuring an embedded device of a first type by means of a host device. The embedded device comprises a computing unit to provide configurable functionality according to input configuration items. The host device comprises an operating system to provide a means for communication with a number of predetermined types of embedded devices. The method includes coupling, via a coupling unit, the embedded device with the host device, including identifying the embedded device to the host device as a second type of device different from the first type or that operates in a different manner from the first type and is comprised of the predetermined types of embedded devices. The method includes presenting or offering a means for entering, retrieving, and supplying configuration items to the embedded device and receiving the configuration items by the computing unit, and performing configuration of the embedded device according to the received configuration items.

A system includes a switch unit that is connected to a host connector of a computer, an embedded controller (EC) that connected to the switch unit, and a management device that includes a device connector and a microcontroller. The device connector is connected to the host connector. The microcontroller is connected to the device connector, and sends external data via the device connector to the EC. When the EC is supplied with electricity, the EC controls the switch unit to establish an electrical connection between the EC and the host connector so as to allow the EC to communicate with the microcontroller through the EC and the host connector to receive the external data from the microcontroller.

The device, method, and system embodiments described in this disclosure (i.e., the teachings of this disclosure) enable an authorization circuit having at least one authorization mechanism to cooperate with an access circuit having at least one key mechanism. Upon successfully authorizing at least one datum communicated from the key mechanism of the access circuit, the authorization circuit is arranged to deliver power having determined characteristics to the access circuit. In at least one embodiment, the authorization circuit is arranged as a circuit wired or wirelessly coupled to a power infrastructure in a building. In at least one embodiment, the access circuit is arranged as a smart power plug arranged to temporarily deliver power to a mobile computing device or other electrically powered device. In some cases, power is only delivered after a user consumes certain multimedia information. In some cases, power that is delivered is delivered for only a short time and is measured.

Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, a removable media (e.g., a memory card, or a USB drive) may be configured to execute instructions with matrix operands and configured with: an interface to receive a video stream; and random access memory to buffer a portion of the video stream as an input to an artificial neural network and to store instructions executable by the deep learning accelerator and matrices of the artificial neural network. Such a removable media can be used to replace an existing removable media used in a surveillance camera to record video or images. The deep learning accelerator can execute the instructions to generate analytics of the buffer portion using the artificial neural network, enabling the surveillance camera that is upgraded via the use of the removable media to provide intelligent services based on the analytics.

Techniques for supporting optical and electrical protocols, such as on the ports of a line card in a network device, are provided. A port on a line card supports optical and electrical connections. The PHY monitors a signal to determine if the transmission connection at the port has changed, such as from optical to electrical, or vice versa. If there has been a change, the PHY is directed to reset a port to correspond to the appropriate transmission connection. By resetting the port, the PHY changes the protocol that is utilized with the signals (e.g., NRZI or 3-Level MLT3).

Systems and methods of controlling a docking station comprise establishing, by the wireless access point, a USB connection tunnelled over a local area wireless network connection with the mobile device, receiving, by the wireless access point over the USB connection, a request for an Internet Protocol (IP) or a Media Access Control (MAC) network address of the display controller, transmitting, by the wireless access point in response to the request, the IP or the MAC network address of the display controller to the mobile device over the USB connection, and receiving, by the wireless access point, the at least video data addressed to the IP or the MAC network address of the display controller and switching the at least video data addressed to the IP or the MAC network address of the display controller directly to the display controller without passing via the USB controller.

A hybrid docking station determines whether native video data exists and can be passed through to a video port or whether a virtual video processor should be activated to provide virtual video data to a video port. For example, a laptop is connected to a hybrid docking station using a USB™ 3.0 connection. The hybrid docking station recognizes that the USB™ 3.0 connection includes a native video data and passes the native video data to a DisplayPort™. By avoiding activating a virtualized video processor and using native video data, the laptop avoids installing software to communicate with the virtualized video processor and communicates with one or more displays using a native video channel. By avoiding installing software, it simplifies IT's and user's usage and experience with universal docking station.

In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.

A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.