A computer readable medium includes a data set with data stored in rows and N columns. Each of the rows is associated with one individual patient. Each of the N columns is associated with one type of data for patients. One or more processors is configured to: initialize missing values in M ones of the N columns with M values for the M ones of the N columns, respectively; generate M mathematical models for the M ones of the N columns having one or more missing values; for each of the rows having one or more missing values, update ones of the M values for the M ones of the N columns; and fill missing values in the M ones of the N columns with the M values, respectively.

A method for key agreement between a first party and a second party over a public communications channel, the method including selecting, by the first party, from a semigroup, a first value “a”; multiplying the first value “a” by a second value “b” to create a third value “d”, the second value “b” being selected from the semigroup; sending the third value “d” to the second party; receiving, from the second party, a fourth value “e”, the fourth value comprising the second value “b” multiplied by a fifth value “c” selected by the second party from the semigroup; and creating a shared secret by multiplying the first value “a” with the fourth value “e”, wherein the shared secret matches the third value “d” multiplied by the fifth value “c”.

A method for key agreement between a first party and a second party over a public communications channel, the method including selecting, by the first party, from a semigroup, a first value “a”; multiplying the first value “a” by a second value “b” to create a third value “d”, the second value “b” being selected from the semigroup; sending the third value “d” to the second party; receiving, from the second party, a fourth value “e”, the fourth value comprising the second value “b” multiplied by a fifth value “c” selected by the second party from the semigroup; and creating a shared secret by multiplying the first value “a” with the fourth value “e”, wherein the shared secret matches the third value “d” multiplied by the fifth value “c”.

The time-of-flight system disclosed herein includes a frequency unwrapping module configured to generate an input phase vector with M phases corresponding to M sampled signals from an object, determine an M−1 dimensional vector of transformed phase values by applying a transformation matrix (T) to the input phase vector, determine an M−1 dimensional vector of rounded transformed phase values by rounding the transformed phase values to a nearest integer, and determine a one dimensional lookup table (LUT) index value by transforming the M−1 dimensional rounded transformed phase values. The index value is input into the one dimensional LUT to determine a range of the object.

Methods, systems and circuits evaluate a subject's risk of developing type 2 diabetes or developing or having prediabetes using at least one defined mathematical model of risk of progression that can stratify risk for patients having the same glucose measurement. The model may include NMR derived measurements of GlycA and a plurality of selected lipoprotein components of at least one biosample of the subject.

Methods, systems and circuits evaluate a subject's risk of developing type 2 diabetes or developing or having prediabetes using at least one defined mathematical model of risk of progression that can stratify risk for patients having the same glucose measurement. The model may include NMR derived measurements of GlycA and a plurality of selected lipoprotein components of at least one biosample of the subject.

Disclosed are methods and systems for performing uncertainty calculations. For example, a numeric value and an error range associated with the numeric value are converted by a processor into a trans-imaginary input dual which is a hybrid of numeric and geometric information having real and complex numbers. A dual calculation is performed using the trans-imaginary input dual to produce a trans-imaginary output dual, and the processor then converts the trans-imaginary output dual to a real number output numeric value that includes both a real number and real number error range or uncertainty associated with that real number.

Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.

Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.

A memory built-in device according to the present disclosure is a memory built-in device including a processor; a memory access controller; and a memory to be accessed in accordance with a process by the memory access controller, wherein the memory access controller is configured to read and write data to be used in an operation of a convolution arithmetic circuit from and to the memory according to designation of a parameter.