Component access control includes: receiving, by an access control module, permissions specifying authorization of physical access to one or more secured components of a computing system by one or more requestors; receiving, by the access control module from a requestor, a request to physically access one of the secured components of the computing system; determining, by the access control module based on the permissions, whether the requestor is authorized to physically access the secured component; and responsive to determining that the requestor is authorized to physically access the secured component, granting the requestor physical access to the secured component while prohibiting the requestor from physically accessing other secured components of the computing system.

An integrated-circuit device comprises a bus system connected to a processor, a plurality of peripherals, each connected to the bus system, hardware filter logic; and a peripheral interconnect system, separate from the bus system and connected to the peripherals. For each peripheral, the hardware filter logic stores a respective value determining whether the peripheral is in a secure state. The peripheral interconnect system provides a set of one or more channels for signalling events between peripherals. At least one channel is a secure channel or is configurable to be a secure channel. The peripheral interconnect system is configured to allow an event signal from a peripheral in the secure state to be sent over a secure channel and to prevent an event signal from a peripheral that is not in the secure state from being sent over the secure channel.

An integrated-circuit device comprises a bus system connected to a processor, a plurality of peripherals, each connected to the bus system, hardware filter logic; and a peripheral interconnect system, separate from the bus system and connected to the peripherals. For each peripheral, the hardware filter logic stores a respective value determining whether the peripheral is in a secure state. The peripheral interconnect system provides a set of one or more channels for signalling events between peripherals. At least one channel is a secure channel or is configurable to be a secure channel. The peripheral interconnect system is configured to allow an event signal from a peripheral in the secure state to be sent over a secure channel and to prevent an event signal from a peripheral that is not in the secure state from being sent over the secure channel.

A system is provided. The system includes a computing resource, a cable insertable into the computing resource, a locking element and a controller. The locking element is configured to assume a locked condition in which the cable is locked to the computing resource or prevented from insertion into the computing resource and an unlocked condition in which the cable is removable from the computing resource and permitted to be inserted into the computing resource. The controller is configured to define rules for users. The rules are associated with respective identifiers (IDs) of each of the users and establish criteria associated with each user for causing the locking element to assume one of the locked and unlocked conditions.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (400). The received address is mapped (402) to a slave address. Default access permissions are associated (404) to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (406). The master-slave connection is enabled (408) if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.

Systems, apparatuses, methods, and computer-readable media are provided for device interface management. A device includes a device interface, a virtual machine (VM) includes a device driver, both to facilitate assignment of the device to the VM, access of the device by the VM, or removal of the device from being assigned to the VM. The VM is managed by a hypervisor of a computing platform coupled to the device by a computer bus. The device interface includes logic in support of a device management protocol to place the device interface in an unlocked state, a locked state to prevent changes to be made to the device interface, or an operational state to enable access to device registers of the device by the VM or direct memory access to memory address spaces of the VM, or an error state. Other embodiments may be described and/or claimed.

In an example, replaceable print apparatus component authentication apparatus comprises a memory and circuitry. An electrical characteristic of the circuitry may be variable in response to a stimulus, and the memory may store data indicative of an expected variation in the electrical characteristic in response to the stimulus which is associated with a variation in capacitance.

In an example, replaceable print apparatus component authentication apparatus comprises a memory and circuitry. An electrical characteristic of the circuitry may be variable in response to a stimulus, and the memory may store data indicative of an expected variation in the electrical characteristic in response to the stimulus which is associated with a variation in capacitance.

One aspect provides an FPGA chip mounted on a printed circuit board (PCB). The FPGA chip can include a joint test action group (JTAG) interface comprising a number of input/output pins and an enablement pin, and a control logic block coupled to the enablement pin of the JTAG interface. The control logic block can receive a control signal from an off-chip control unit and control a logical value of the enablement pin based on the received control signal, thereby facilitating the off-chip control unit to lock or unlock the JTAG interface. The FPGA chip can further include a detection logic block to detect an unauthorized access to the FPGA chip. An input to the detection logic is coupled to the enablement pin, and a conductive trace coupling the input of the detection logic block and the enablement pin is situated on an inner layer of the PCB.