A technique includes providing a security monitor to at least detect a penetration attack on a circuit assembly that contains the security monitor. The technique includes inhibiting success of the penetration attack, including flexibly mounting the security monitor to the circuit assembly to allow the security monitor to move in response to the security monitor being contacted during the penetration attack.

A technique includes providing a security monitor to at least detect a penetration attack on a circuit assembly that contains the security monitor. The technique includes inhibiting success of the penetration attack, including flexibly mounting the security monitor to the circuit assembly to allow the security monitor to move in response to the security monitor being contacted during the penetration attack.

A data-entry device includes an upper cover to which a capacitive pad is affixed through the exterior. The capacitive pad has at least one flexible security element having at least one electrical track connected to a cut-detection module in the device. The shape and the mounting of the at least one security device is adapted to exert a force on the internal face of the upper cover.

A data-entry device includes an upper cover to which a capacitive pad is affixed through the exterior. The capacitive pad has at least one flexible security element having at least one electrical track connected to a cut-detection module in the device. The shape and the mounting of the at least one security device is adapted to exert a force on the internal face of the upper cover.

Examples of an apparatus, method, and instructions included on a machine-readable non-transitory storage medium are disclosed herein. in an example of the method, a first state is provided to enable a camera to record an image, a second state is provided to disable the camera, and a third state is provided to permit the camera to be enabled and disabled. Also in this example of the method, a button is actuated in the third state to an on position to enable the camera to record an image or an off position to disable the camera. Additionally in this example of the method, a signal is generated via an input device in the on position of the button to enable the camera to record an image or disable the camera.

For a secure device chamber, the device chamber is disposed in a chassis and includes a device port. A door latches to obstruct access to the device chamber. A logic circuit receives an uninterrupted power supply from a computer, stores a device access value, and unlatches the door in response to activation of a chamber eject button and a device access value not being a device secure mode.

For a secure device chamber, the device chamber is disposed in a chassis and includes a device port. A door latches to obstruct access to the device chamber. A logic circuit receives an uninterrupted power supply from a computer, stores a device access value, and unlatches the door in response to activation of a chamber eject button and a device access value not being a device secure mode.

Embodiments are directed to an IC device comprising a set of N elements, and an interconnect system for enabling communication between the set of elements. Each element of the set of elements is configured according to a first communication plan to receive attestation data of each other element of the set of elements. Upon receiving the attestation data the element may determine whether each of the received attestation data from the other elements match an attestation pattern as defined in the first communication plan. In case the received attestation data match the first communication plan, the element may determine whether the received attestation data is attested by N−1 elements of the set of elements. In case the attestation data is attested by N−1 elements of the set of elements, the element may indicate the presence of the set of elements before the time interval has lapsed.

A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.

A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.