Systems and methods for application specific integrated circuit design using Chronos links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Systems and methods for application specific integrated circuit design using Chronos links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

The present disclosure provides an electronic device, a method for generating a package drawing, and a computer readable storage medium. The electronic device includes a display device and a processor, the processor is configured to obtain a type of the element and size parameters corresponding to the element input by a user; determine a size and a position of each of pads corresponding to the element according to the type of the element and the size parameters corresponding to the element, and draw the pads; determine coordinates of endpoints of an entity layer corresponding to the element, and draw the entity layer; determine coordinates of endpoints of a height layer corresponding to the element, and draw the height layer; and determine coordinates of endpoints of a screen layer corresponding to the element, and draw the screen layer.

A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes generating a second circuit representation model based on updating the plurality of impedance values between the one or more port-pairs based on a second value for one or more parameters of the plurality of parameters of the circuit component, and updating the second circuit representation model by tuning the updated plurality of impedance values of the between the one or more port-pairs based on a predetermined use context of the circuit component in a circuit.

Methods for implementing or synthesizing functions in hardware and fixed-function hardware include generating a look-up table, LUT, representing the function and then applying a transform to the LUT to transform the LUT into a plurality of derived LUTs. The transform may be applied recursively. A hardware design implementing each of the derived LUTs in fixed-function hardware logic, along with a logic unit that performs the inverse transform, is then created.

An electronic system can be used to monitor temperature. The electronic system can include a characterized dielectric located adjacent to a plurality of heat-producing electronic devices. The electronic system can also include a leakage measurement circuit that is electrically connected to the characterized dielectric. The leakage measurement circuit can be configured to measure current leakage through the characterized dielectric. The leakage measurement circuit can also be configured to convert a leakage current measurement into a corresponding output voltage. A response device, electrically connected to the leakage measurement circuit can be configured to, in response to the output voltage exceeding a voltage threshold corresponding to a known temperature, initiate a response action.

An electronic system can be used to monitor temperature. The electronic system can include a characterized dielectric located adjacent to a plurality of heat-producing electronic devices. The electronic system can also include a leakage measurement circuit that is electrically connected to the characterized dielectric. The leakage measurement circuit can be configured to measure current leakage through the characterized dielectric. The leakage measurement circuit can also be configured to convert a leakage current measurement into a corresponding output voltage. A response device, electrically connected to the leakage measurement circuit can be configured to, in response to the output voltage exceeding a voltage threshold corresponding to a known temperature, initiate a response action.

A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

Methods and systems are provided for protecting a circuit design for an integrated circuit. Logic circuits are identified in at least a portion of the circuit design for replacement. The logic circuits in the circuit design are replaced with a bitstream and configurable circuits that comprise memory circuits. A transformed circuit design is generated for the integrated circuit that comprises the configurable circuits. The configurable circuits in the transformed circuit design perform logic functions of the logic circuits when the bitstream is stored in the memory circuits in the configurable circuits.