Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an iterative approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim. This approach can be both computationally efficient and accurate and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network.

A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

In some embodiments, techniques are provided for verifying that a fabrication system can fabricate a proposed segmented design. A paintbrush pattern that represents capabilities of the fabrication system is determined. One or more forbidden patterns that the fabrication system is not capable of fabricating are determined based on the paintbrush pattern. The proposed segmented design is then searched for the forbidden patterns. If any forbidden patterns are found, the proposed segmented design is determined to not be fabricable by the fabrication system. If no forbidden patterns are found, then the proposed segmented design is determined to be fabricable by the fabrication system.

A programmable device includes a functional module, a pre-allocation manager, a first connection line, and a second connection line, wherein the pre-allocation managers are connected by the first connection lines, and the pre-allocation managers are connected to the functional modules by the second connection lines; the first connection lines are used for data transmission between the pre-allocation mangers, and a transmission direction is determined according to the configuration; the second connection lines are used for data transmission between the pre-allocation managers and the functional modules; the pre-allocation mangers are used for data transmission between the first connection lines and for data transmission between the first connection lines and the functional modules. The first connection lines are configured as connection line segments for transmission in both directions, and a wiring structure is designed in a direction and shape meeting wiring requirements.

A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes acquiring, based on a compression model that is acquired by learning processing on a set of data generated by using a combination of values of variables and that compresses dimensions of data, a point corresponding to data generated by using a predetermined combination of the values of variables within a compressed space; acquiring, based on the point corresponding to the data generated by using the predetermined combination, a target point within the space corresponding to a target value of a characteristic changing in accordance with the values of variables, and a regression model within the space for a predetermined variable of variables, a change amount of the predetermined variable; and changing the value of the predetermined variable included in the predetermined combination by using the change amount.

A multicore processing environment (MCPE) is disclosed. In embodiments, the MCPE includes multiple processing cores hosting multiple user applications configured for simultaneous execution. The cores and user applications share system resources including main memory and input/output (I/O) domains, each I/O domain including multiple I/O devices capable of requesting inbound access to main memory through an I/O memory management unit (IOMMU). For example, the IOMMU cache associates unique cache tags to each I/O device based on device identifiers or settings determined by the system registers, caching the configuration data for each I/O device under the appropriate cache tag. When each I/O device requests main memory access, the IOMMU cache refers to the appropriate configuration data under the corresponding unique cache tag. This prevents contention in the IOMMU cache caused by one device evicting the cache entry of another, minimizing interference channels by reducing the need for main memory access.

A multicore processing environment (MCPE) is disclosed. In embodiments, the MCPE includes multiple processing cores hosting multiple user applications configured for simultaneous execution. The cores and user applications share system resources including main memory and input/output (I/O) domains, each I/O domain including multiple I/O devices capable of requesting inbound access to main memory through an I/O memory management unit (IOMMU). For example, the IOMMU cache associates unique cache tags to each I/O device based on device identifiers or settings determined by the system registers, caching the configuration data for each I/O device under the appropriate cache tag. When each I/O device requests main memory access, the IOMMU cache refers to the appropriate configuration data under the corresponding unique cache tag. This prevents contention in the IOMMU cache caused by one device evicting the cache entry of another, minimizing interference channels by reducing the need for main memory access.

A method of path routing in a multilayered structure including layers and one or more links formed between adjacent layers includes identifying path connection elements included in each layer of a multilayered structure with layers that can have at least one links between adjacent layers, generating, for each layer of the multilayered structure, an embedded frame including the path connection elements identified in each layer of the multilayered structure, generating a topological frame including an outer boundary enclosing one or more punctures formed by the links among the plurality of path connection elements included in the embedded frame and one or more local path points arranged on a boundary of each of the one or more punctures, and generating a circular frame including a single circular closed curve by merging the boundary of each of the one or more punctures and the outer boundary of the topological frame.

Predicting power usage of a chip may include receiving placement data describing a placement, within the chip, of a plurality of logical components of the chip; providing the placement data as an input to a neural network; and determining, by the neural network, based on the placement data, a predicted power usage of the chip.

A method and computing system operable for displaying a first routing diagram on a display. The first routing diagram is a member of a first set of routing diagrams that includes multiple different routing diagrams. Displaying the first routing diagram includes displaying a user-selectable control and a first portion of a particular routable component within the first routing diagram. The user-selectable control indicates that the particular routable component continues on a second routing diagram. An additional function include determining, by one or more processors, a selection of the user-selectable control occurs while the first routing diagram is displayed on the display. A further function includes displaying the second routing diagram on the display in response to determining the selection of the user-selectable control occurs while the first routing diagram is displayed on the display. Displaying the second routing diagram includes displaying a second portion of the particular routable component.