Patent classifications
G06F2101/10
Functional unit capable of executing approximations of functions
A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X2.sup.2. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.
Systems and methods for computing mathematical functions
Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like); and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes; wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes. SIN and COS are also computed using the pipeline according to the approximation ((1)^IntX)*Sin(*Min(FracX, 1.0FracX)/Min(FracX, 1.0FracX). A pipeline portion approximates Sin(*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x1)/(x1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed.
Simulation method for characteristics of transistor, simulation method for characteristics of electronic circuit including transistor, and nontransitory recording medium that stores simulation program for characteristics of transistor
A simulation method includes a process of calculating a transient charge density q.sub.T of trapped charges after applying a voltage between a gate electrode and a semiconductor layer of a transistor, the charge density q.sub.T being calculated with a time variance of the charge density q.sub.T being expressed by a function obtained by superimposing multiple exponential functions having mutually different time constants.
METHOD AND APPRATUS WITH VARIABLE PARAMETER EXPRESSION
Disclosed are a method of expressing a parameter variably and an apparatus for the same. A neural processor apparatus includes: a comparator configured to read a value of a fixed-length exponent of a previously-converted parameter value and obtain mantissa-length information of a mantissa, wherein the mantissa-length information is obtained from a mapping table based on being mapped to the value of the exponent; a shifter configured to read the mantissa of the previously-converted parameter value and use the mantissa-length information to convert a structure of the previously-converted parameter value; and the mapping table, in which the mantissa-length information of the mantissa is mapped to the value of the exponent.
DEVICES FOR DIGITAL-DOMAIN TEMPERATURE COMPENSATION IN LOGARITHMIC TRANSIMPEDANCE AMPLIFIERS
Technologies are provided to calculate a logarithm of an input current to a logarithmic transimpedance amplifier device at a particular temperature. The logarithm of the current is calculated in digital domain based on sampling of analog signals that are internal to the logarithmic transimpedance amplifier device. The sampling can be performed, in some cases, by an analog-to-digital converter device integrated into the logarithmic transimpedance amplifier device. The calculation in digital domain is performed by one or more processor external to the logarithmic transimpedance amplifier device. The calculation includes a determination of a temperature compensation factor based on an internal analog signal indicative of temperature of the logarithmic transimpedance amplifier device. The temperature compensation factor permits removing temperature dependence from a logarithmic output voltage originating from the input current. Operating in the digital domain permits applying corrections that account for residual leakage current and an emitter-resistance correction at high input currents.
DEEP LEARNING CONVOLUTION ACCELERATION METHOD USING BIT-LEVEL SPARSITY, AND PROCESSOR
The present application provides a deep learning convolution acceleration method using bit-level sparsity and a processor. Comprises: selecting the maximum sum of the exponents from all data pairs to be convolved as a maximum exponent; arranging mantissas of the original weights in a computation sequence to form a weight matrix, and uniformly aligning each row of the weight matrix to the maximum exponent and removing slack bits to obtain a reduced matrix, allowing essential bits in each column of the reduced matrix to fill the vacancies according to the computation sequence, after removing null rows in the intermediate matrix, placing zeros at vacancies of the matrix to obtain an interleaved weight matrix, sending the weight segments in each row of the interleaved weight matrix and the mantissa of the corresponding activation to an adder tree for processing summation, by shifting and adding the sum result to obtain a convolution result.
FAST AND RESOURCE-EFFICIENT APPROXIMATION FOR THE EXPONENTIAL FUNCTION
A method for computing an approximate value A of the exponential function e.sup.x of an argument x. The method includes: approximating e.sup.x with a Taylor expansion T around x=0 that includes a predetermined number n of terms with i-th powers x.sup.i of the argument x divided by the respective factorial of i, with i=1, . . . , n, and in the computation of each term, approximating the factorial of i to the nearest power of 2, p(i!).
System, Method, and Computer Program Product for Multi-Head Posterior Based Pre-Trained Model Evaluation
Systems, methods, and computer program products for multi-head posterior based pre-trained model evaluation are provided. The system includes at least one processor configured to: generate an embedding dataset based on a pre-trained model, the embedding dataset including a plurality of embeddings representing a plurality of entities; cluster each entity of the plurality of entities based on a feature dataset, resulting in a plurality of clusters; and generate a metric for the pre-trained model based on a posterior probability of each entity of the plurality of entities and the plurality of clusters.
Systems for automated blast design planning and methods related thereto
A system, method, or apparatus for generating a blast plan that can receive blast data comprising geological properties of a blast site, blasthole parameters, and available explosive product. A pattern footage can be determined based on a relationship between the face height, the specific energy of the available explosive product, and the geological properties of the bench. The burden and spacing can be determined from the pattern footage.