Systems and methods for integrated circuit (IC) analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure are described. An IC design may be represented using a set of storage areas, where each storage area may be stored in a contiguous block of storage and may correspond to a portion of the IC design. An analysis application may be executed on the IC design, where a subset of the set of storage areas that is used by the analysis application may be retrieved on-demand.

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: receive information representing technical requirements for the analogue circuit; identify, based on the received information, a plurality of circuit portions for forming the analogue circuit; determine, for each circuit portion of the plurality circuit portions, respective technical criteria for that circuit portion; produce a set of designs comprising a respective design for each circuit portion; for at least one circuit portion of the plurality of circuit portions obtain information relating to parasitics that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion; adapt the design of at least one circuit portion based on the obtained information relating to parasitics; and output a complete circuit design including at least one circuit portion adapted based on obtained information relating to parasitics.

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: identify a plurality of circuit portions for forming the analogue circuit; determine for each circuit portion respective technical criteria; and provide the respective technical criteria to at least one of a plurality of secondary design units. Each of the plurality of secondary design units is configured to: design a respective circuit portion based on the technical criteria for that respective circuit portion; and output a resulting initial design of the respective circuit portion. After at least an initial design of a given circuit portion has been completed by at least another one of the secondary design units, at least one of the secondary design units is configured to adapt its output initial design based on a context of its corresponding circuit portion.

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: identify a plurality of circuit portions for forming the analogue circuit; determine for each circuit portion respective technical criteria; and provide the respective technical criteria to at least one of a plurality of secondary design units. Each of the plurality of secondary design units is configured to: design a respective circuit portion based on the technical criteria for that respective circuit portion; and output a resulting initial design of the respective circuit portion. The primary design unit is further configured to obtain, a set of designs comprising a respective design for each circuit portion, generate, at least an initial design for the analogue circuit, based on the set of designs, simulate an analogue circuit based on the generated design and verify whether or not the analogue circuit meets the technical requirements for the analogue circuit.

Methods and apparatus to facilitate 3D object visualization and manipulation across multiple devices are disclosed. Example apparatus disclosed herein include a viewpoint determiner, a visible shard determiner, and a laminate assembler. The viewpoint determiner determines a viewpoint location of a viewpoint corresponding to a viewing device, the viewpoint location being in a reference frame of a three-dimensional (3D) model. The visible shard determiner determines a visible shard set of the 3D model based on the viewpoint location. The laminate assembler generates a two-dimensional (2D) image of the visible shard set.

An engineering support system that supports engineering of a process control system, includes: a storage; and a processor connected to the storage and that: transforms design drawings into semantic models and outputs the semantic models to the storage; and generates a combined semantic model by combining the semantic models based on a degree of similarity among the semantic models and outputs the combined semantic model to the storage, wherein each of the semantic models is expressed by first information indicating elements included in the design drawings and second information indicating a relationship between the elements.

A system comprising a set of multiple simulators. Either: a) each simulator performs a different respective trial of a simulation of a same physical phenomenon, or b) each simulator comprises a different instance of a piece of software arranged to automatically perform a different trial of a simulation of using a same functionality of the software. The system further comprises: a control interface configured to collect respective simulation results from at least some of the simulators, and return the collected simulation results to a consumer. The consumer comprises a machine learning algorithm arranged to train a machine learning model using the simulation results supplied by the control interface. The control interface is further configured to detect a state of each of the simulators, and in response to detecting a faulty state of a faulty simulator from amongst the set of the simulators, reset the faulty simulator.

Systems and methods are disclosed for linking a two-dimensional (2D) design image to a three-dimensional (3D) design model. One method comprises receiving a 2D design document and a 3D design file, the 2D design document comprising a 2D design image and the 3D design file comprising a 3D design model including design elements. The 3D design model is converted to a coded 2D design image. A unique identifier is determined for each design element based on the coded 2D design image, and stored in association with the respective design element in the 3D design file. Upon a user selection of a point in the 2D design image, detailed information on the design element corresponding to the user-selected point may be retrieved from the 3D design file. The retrieval may be based on matching a code associated with the user-selected point to a unique identifier in the 3D design file.

A method and system provide the ability to asynchronously collaborate on a model of an infrastructure project. The model is acquired and view settings for the model are captured. The view settings include a feature highlight that provides display attributes/settings for objects and/or features of the model, a camera position providing second settings relating to a camera view of the model, and a data view providing third settings regarding a view of the model data. The view settings are associated with a link. The link is transmitted/provided from a sender to a recipient. The link enables rehydration of a live model based on the captured view settings thereby presenting a state and view settings of the model specified by the sender.

Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.