The present invention provides a cable planning method based a fast marching method applied with simulated annealing (FMM/SA) algorithm. In the FMM/SA algorithm-based cable planning method, the FMM used to obtain the optimal submarine cable path with the lowest life-cycle cost, and the SA algorithm is used to continuously adjust the weight of each design consideration with the aim to achieve an optimal cable path that is as close as possible to a real-life cable path which has a history of cost-effectiveness and resilience. The set of weights contributed to the optimal cable path is then used as an optimal set of weights of design considerations for cable path planning. The FMM/SA algorithm-based cable planning method can provide a computationally effective approach which has lower computation costs and better performance in generating cable paths with optimal life-cycle cost and reliability.

The invention relates to the technical field of computer-aided design of integrated circuits, and provides a two-step X-architecture Steiner minimum tree construction method for very large scale integration (VLSI). Based on the advantages of an X-architecture model and a particle swarm optimization technique, the method is implemented through two steps: (1) the stage of social learning discrete particle swarm search, which comprises: using an edge-vertex encoding strategy capable of maintaining optimal topological information of particles, designing a fitness function taking wirelength into consideration; and using a chaotic decreasing mutation strategy and a new social learning strategy to design a new discrete particle swarm update formula; and (2) a stage of wirelength optimization, which comprises: designing a local topological optimization strategy to minimize the wirelength of an X-architecture Steiner tree. The method guarantees short total wirelength of nets and has high stability, thus being able to construct a high-quality X-architecture Steiner minimum tree.

A machine learning-based method for designing a high-strength high-toughness steel, including: (S1) obtaining data and filling in missing parts to form a data set; (S2) selecting feature data in the data set to form a standard data set; (S3) constructing two machine learning models of the high-strength high-toughness steel; (S4) completing training after the two models are evaluated to be qualified; (S5) finding frontier points, drawing a Pareto front, and distinguishing a known region and a feature space; (S6) in the feature space, setting a step for the feature data, drawing a grid space, and performing multiple training predictions on each grid point by using the models, to obtain predicted Gaussian distributions of two objectives; and (S7) searching for an expected improvement point through an efficient global optimization algorithm, and obtaining design parameter values of corresponding features.

An approach is provided for estimating the optimal number and mixture of types of electric vehicle (EV) charging stations (EVCS) at one or more points of interest (POIs). A method includes generating, based on an EV adoption model, an EV adoption prediction. The method includes generating, based on a mobility simulation model, a driver-type prediction that predicts percentages of EV drivers qualifying for various EV driver types. The method includes generating, based on the EV adoption prediction, the driver-type prediction, and a visitation model, a visitation prediction that predicts how many EV drivers of each type of EV driver will visit the POI. The method includes determining and displaying, based on how many EV drivers of each type of EV driver is predicted to visit the POI, for each type of EV charging station of a plurality of types of EV charging stations, an optimal number of EVCS to install.

Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.

A system including one or more processors and one or more non-transitory computer-readable media storing computing instructions configured to run on the one or more processors and perform certain acts. The acts can include obtaining a route for delivering one or more orders in a tri-temp trailer from a distribution center to physical stores in a sequence of stops. The route can have an associated assignment of stack groups comprising stacks of pallets. The acts also can include determining a load design for the stacks in the tri-temp trailer based on the sequence of the stops in the route, such that unloading each of the stacks is minimized when the tri-temp trailer delivers the orders to the physical stores. The acts additionally can include outputting the load design to cause the stacks to be loaded in the tri-temp trailer according to the load design for delivery to the physical stores in the sequence of stops. The load design can specify a respective floor spot assignment for each of the stacks. Other embodiments are described.

A method, apparatus, computer device, and storage medium for automatic design of analog circuits based on tree structure. The method includes: setting the maximum height and growth direction of the tree structure; randomly calling the node from the function node library as the parent node; randomly calling the node from the function node library and the port node library as the child according to the growth direction node; if the child node is a terminal node, generating a tree structure; checking the tree structure, if the tree structure satisfies the preset conditions, obtaining the circuit topology and device parameter that conform to the circuit rules; evolving the circuit topology and device parameter to generate an analog circuit. The embodiments achieve the effect of making the tree structure of the designed analog circuit more reasonable.

A method including generating a plurality of synthetic images of a material, where each synthetic image from among the plurality of synthetic images is associated with a feasibility value greater than a threshold synthetic feasibility value. The method includes determining, for each synthetic image from among the plurality of synthetic images, one or more material properties of the material and one or more process parameters of the material based on the synthetic image and generating a plurality of data points and a pareto surface based on the one or more material properties and the one or more process parameters. The method includes selecting a target data point based on the plurality of data points and a distance between a set of data points from among the plurality of data points and the pareto surface.

Training of a machine learning model used to infer estimated delays of circuit routes during placement and routing of a circuit design. Training can include selecting sample pairs of source pins and destination pins of an integrated circuit (IC) device, and determining respective delays of shortest paths that connect the source pins to the destination pins of the sample pairs based on a resistance-capacitance model of wires that form the shortest paths on the IC device. Respective sets of features are determined for the shortest paths, and the model is trained using the respective sets of features and the respective delays as labels. The machine learning model can be provided to an electronic design automation tool for estimating delays.

A global optimization tool may be used to predict characteristics of a multiple ply layered composite as a condition of one or more continuous variables and/or one or more binary variables. For example, the global optimization tool may predict characteristics of a composite for a large range of fiber orientation angles of each of layer of the ply. The optimization tool may include solving a mixed integer nonlinear programming (MINLP) model to obtain a multiple ply layered composite design that is optimized relative to objectives, such as areal weight and cost. Thus, the global optimization tool may be able to identify composite designs with lower areal weight and/or lower cost than the composite designs identified by prior art trial and error methods or heuristic algorithms. When a composite design is identified as meeting certain criteria that are input to the global optimization tool, that composite design may be manufactured.