A piping diagram creation device is provided configured to: generate virtual pipelines, the virtual pipelines being identified by characteristic evaluation data expressed as a sequence of numbers with an assembling angle θi of assembling portions of the respective straight pipes and cut pipes allocated between respective intersections, and an adjustment margin Lj of the cut pipe length as variables; calculate an evaluation value of each virtual pipeline based on a difference value and so on between the total number of intersections and control points and the number of intersections and control points having an error between the virtual pipeline and each intersection and between the virtual pipeline and each control point at or below a predetermined threshold, the latter number being a continuous count from the start point; and generate a pipeline assembling diagram based on one virtual pipeline with an excellent evaluation value.

Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An iterating module iterates through the time steps to determine values for physical quantities of the body at the end of the simulation period. Preferably one particle of the body is assigned to each node of the grid. For moving boundary processes, boundary movement can be represented simply by changing the particle type assigned to various nodes of the grid as the boundary advances.

Provided are a drawing creation method, a wire harness manufacturing method, and a drawing creation device. A drawing showing a wire harness is created by the drawing creation method. The wire harness is configured with wires bundled together. The wire harness includes wire branch points and branch lines. The drawing is created based on information including following (1) to (3) and at least one of following (4) or (5): (1) a path of the wire harness in a movable body, (2) a distance between path branch points where the path branches, (3) a length from each path branch point to a corresponding connection target of the wire harness, (4) identification information of the connection target of the wire harness, (5) identification information of the connection target of each wire. The drawing reflects a distance between the wire branch points and a length of each branch line.

Embodiments relate to schematic overlays describing modification to a base design for exploring modification or verification of the base design. Test circuitry may be modified or inserted without effecting the change in a base design schematics. The modifications to the base design schematics are also highlighted in views at a level of hierarchy where the modifications were made as well as at a higher levels of circuit abstraction. By using schematic overlays, modification to the base design can be avoided while creating a testbench.

A method and a system for verifying an integrated circuit stack having at least one silicon photonic device is introduced. A dummy layer and a dummy layer text are added to a terminal of at least one silicon photonic device of the integrated circuit. The method may perform a layout versus schematic check of the integrated circuit including the dummy layer and the dummy layer text.

Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.

Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with reference to the abstraction scope with the layout editing mechanism. In addition, these techniques further generate a symbolic representation for the layout circuit component by reproducing at least some of the first data in the layout and perform one or more layout operations on the symbolic representation to improve the layout and to generate a result set for the one or more layout operations.

A device may receive information identifying a model including information associated with elements included in the model. The device may cause the model to be executed, and may collect data associated with executing the model. The device may determine performance information based on the collected data. The performance information may be associated with the elements included in the model. The device may generate a heat map based on the performance information. The heat map may associate an element, of the elements, with a visual representation indicating performance information, associated with the element, based on a heat map scale. The heat map scale may relate the performance information, associated with the element, to performance information associated with another element. The heat map may be a graphical interface that includes a graphical representation of the element and a graphical representation of the other element. The device may provide the heat map.

Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Examples can include a system for generating a spool sheet. A user can select multiple components on a graphical user interface (“GUI”). Then they can select an option to create a spool sheet. The system can determine a list of components in the selection for use in a bill of materials. This can be included in a spool page that includes a printable spool sheet region. Within the spool sheet region, the GUI can display a view of the selected components at a location indicated by an anchor node of the template.