The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

A method, a system, and non-transitory computer readable medium for level package routing are provided. The method includes performing triangulation on a set of nets to generate a routing resource graph. The objects of the set of nets are represented by a respective center point during triangulation. The method also includes generating a route between the objects of the set of nets based on at least a total cost. The total cost is determined based on at least the routing resource graph. The method also includes altering the route based on a determination that a constraint rule is unmet and outputting routing information comprising the route for the set of nets.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

An apparatus is disclosed. The apparatus comprises an integrated circuit (IC) package including a plurality of ICs; a non-volatile memory to store configuration information comprising settings that define an operation of the plurality ICs and a configuration register to receive configuration bits from the non-volatile memory representing a final configuration for the package

Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.

Computer-implemented systems and methods are described herein for determining mechanical properties of an electronic assembly. An input specification for a model of the electronic assembly is received, wherein the input specification includes a compressible body and a surrounding component in the electronic assembly. A geometric interference between the compressible body and the surrounding component is identified. A displacement is generated for the compressible body to account for the geometric interference. A non-linear contact is then generated between the displaced compressible body and the surrounding component. The model is updated with the displacement and the non-linear contact. Then, a resulting force equilibrium is determined within the electronic assembly based on the updated model, wherein the resulting force equilibrium is determined by removing the displacement from the updated model.

A method of warpage-aware floorplanning for heterogeneous integration structure is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a performing a layout partitioning to divide a layout into a plurality of grids; performing an initial floorplanning by assigning first geometric relations between a plurality of dies such that an effective material of each grid of the plurality of grids is determined; performing a global floorplanning to change the first geometric relations between the plurality of dies to second geometric relations to optimize warpage effect of the heterogeneous integration structure; and performing a detailed floorplanning to determine die order of placement based on material differences between the plurality of dies and an interposer.

Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

The present invention provides a system and method for optimizing BoM cost of platform SoC in mobile devices. The system (100) comprises a CPU with SIMD extensions wherein video codec encoder/decoder module is implemented (101), and another CPU with SIMD extensions instead of DSP/VLIW core wherein post-processing filtering module (Deblocking filter) (102) module is implemented. Replacing DSP/VLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed is either case (deblocking filter on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.