Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

A method, a system, and non-transitory computer readable medium for level package routing are provided. The method includes performing triangulation on a set of nets to generate a routing resource graph. The objects of the set of nets are represented by a respective center point during triangulation. The method also includes generating a route between the objects of the set of nets based on at least a total cost. The total cost is determined based on at least the routing resource graph. The method also includes altering the route based on a determination that a constraint rule is unmet and outputting routing information comprising the route for the set of nets.

Computer-implemented systems and methods are described herein for determining mechanical properties of an electronic assembly. An input specification for a model of the electronic assembly is received, wherein the input specification includes a compressible body and a surrounding component in the electronic assembly. A geometric interference between the compressible body and the surrounding component is identified. A displacement is generated for the compressible body to account for the geometric interference. A non-linear contact is then generated between the displaced compressible body and the surrounding component. The model is updated with the displacement and the non-linear contact. Then, a resulting force equilibrium is determined within the electronic assembly based on the updated model, wherein the resulting force equilibrium is determined by removing the displacement from the updated model.

A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

This disclosure relates to system and method for generating an encapsulated error signature during functional simulation. The method includes receiving at least one error descriptor notification message from at least one of a plurality of testbench components. Each of the at least one error descriptor notification message includes values corresponding to a plurality of error attributes including error ranking, error code, error message, and error score. The method further includes iteratively updating in real-time, a plurality of arrays based on values corresponding to one or more of the plurality of error attributes, in response to receiving each of the at least one error descriptor notification message. The method further includes iteratively generating in real-time, an encapsulated error signature based on each of the error ranking, the error code, and an error count associated with the error code derived from one or more of the plurality of arrays.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 2633 mm, using pick-and-place assembly.

Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network. The trained predictor can be used to determine a temperature rise and then can be appended to a system level thermal profile of the IC to generate a detailed thermal profile of the IC.

Provided is a flow analysis method capable of predicting a flow state of a composite resin material by taking into account a change in filler dispersion degree of the composite resin material. In a flow analysis method for a composite resin material having a filler and a resin, in a certain process of identifying a region in which the composite resin material flows and analyzing a flow, an exothermic reaction speed of the composite resin material in the region is computed using a filler dispersion degree in the composite resin material, a temperature and the filler dispersion degree of the composite resin material in the region is computed using the computed exothermic reaction speed, and an exothermic reaction speed in a process subsequent to a process is computed using the computed filler dispersion degree.

Systems and methods are disclosed for pad ring generation for integrated circuits. For example, a method may include accessing a pad ring configuration data structure, wherein the pad ring configuration data structure declares rules for inputs and outputs of an integrated circuit using a scripting language; based on the pad ring configuration data structure, automatically generating an integrated circuit design data structure that encodes a physical design for the integrated circuit that includes a pad ring with bumps satisfying the rules for inputs and outputs of the integrated circuit and also includes a placeholder for additional logic circuits, wherein the placeholder includes connections to one or more input drivers of the pad ring and to one or more output drivers of the pad ring; and transmitting, storing, or displaying the integrated circuit design data structure.

The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.