A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.

A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular connection patterns between structural components (e.g., backbone or fishbone), the placement, width, direction or layer of specific structural components, and properties of structural components relative to other components. These structural directives are implemented generally during routing, such as through design constraints, which allows the router to locally optimize the design (e.g., for cost or wire length) while considering the structural intentions of the designer. The system can also learn and replicate customization patterns based on existing layout templates by comparing connectivity information to that of existing layout templates and applying applicable structural directives.

Embodiments include simulating a design under test on an electronic device. Aspects include running a test program on the design under test and capturing inputs into the design under test. Aspects also include storing the inputs into the design under test in a storage device. Responsive to determining that an event has occurred during execution of the test program, aspects include halting the test program on the design under test. Aspects further include enabling a user via a user interface to determine a cause of the event by performing a simulation of the design under test using the inputs stored in the storage device.

Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Embodiments include simulating a design under test on an electronic device. Aspects include running a test program on the design under test and capturing inputs into the design under test. Aspects also include storing the inputs into the design under test in a storage device. Responsive to determining that an event has occurred during execution of the test program, aspects include halting the test program on the design under test. Aspects further include enabling a user via a user interface to determine a cause of the event by performing a simulation of the design under test using the inputs stored in the storage device.