Verifying a product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the product.

Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.

Novel tools and techniques in a telecommunication network are provided for implementing a data link layer control plane that may comply with the Ethernet standard and with sub-millisecond transmission control capabilities across multiple dis-similar technologies and bandwidth links. The framework provides a dynamic modular traffic control function insertion, removal, mapping function by having interpreter functions in the protocol agents that can map states and commands to sub-service chain functions that are configured per path and quality of service (QoS) flows. The control protocol provides high levels of resiliency and reliability by having a replicating function that transmits the same control protocol frames across multiple links simultaneously. The agents are multi-chassis capable and support hitless service impacts for administrative changes. Control plane messages may be encoded as a data plane frame and be transmitted at a high rate using the data plane.

Novel tools and techniques in a telecommunication network are provided for implementing a data link layer control plane that may comply with the Ethernet standard and with sub-millisecond transmission control capabilities across multiple dis-similar technologies and bandwidth links. The framework provides a dynamic modular traffic control function insertion, removal, mapping function by having interpreter functions in the protocol agents that can map states and commands to sub-service chain functions that are configured per path and quality of service (QoS) flows. The control protocol provides high levels of resiliency and reliability by having a replicating function that transmits the same control protocol frames across multiple links simultaneously. The agents are multi-chassis capable and support hitless service impacts for administrative changes. Control plane messages may be encoded as a data plane frame and be transmitted at a high rate using the data plane.

Novel tools and techniques in a telecommunication network are provided for implementing a data link layer control plane that may comply with the Ethernet standard and with sub-millisecond transmission control capabilities across multiple dis-similar technologies and bandwidth links. The framework provides a dynamic modular traffic control function insertion, removal, mapping function by having interpreter functions in the protocol agents that can map states and commands to sub-service chain functions that are configured per path and quality of service (QoS) flows. The control protocol provides high levels of resiliency and reliability by having a replicating function that transmits the same control protocol frames across multiple links simultaneously. The agents are multi-chassis capable and support hitless service impacts for administrative changes. Control plane messages may be encoded as a data plane frame and be transmitted at a high rate using the data plane.

Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections. In some embodiments, the main die and the IO dies make all connections through microbumps on the silicon interposer and some microbumps connect to external components using through-silicon vias (TSVs). The microbumps of the main die, in some embodiments, are arranged so that they are mirrored on either side of the main die and rotationally invariant under a 180 degree rotation. IO dies, in some embodiments, are mounted in a first orientation to connect to a first side of the main die and a second rotated (by 180 degrees) orientation to connect to a second opposite side of the main die.

Verifying a product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the product.

An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.

Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections. In some embodiments, the main die and the IO dies make all connections through microbumps on the silicon interposer and some microbumps connect to external components using through-silicon vias (TSVs). The microbumps of the main die, in some embodiments, are arranged so that they are mirrored on either side of the main die and rotationally invariant under a 180 degree rotation. IO dies, in some embodiments, are mounted in a first orientation to connect to a first side of the main die and a second rotated (by 180 degrees) orientation to connect to a second opposite side of the main die.

A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of structural directives that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular connection patterns between structural components (e.g., backbone or fishbone), the placement, width, direction or layer of specific structural components, and properties of structural components relative to other components. These structural directives are implemented generally during routing, such as through design constraints, which allows the router to locally optimize the design (e.g., for cost or wire length) while considering the structural intentions of the designer. The system can also learn and replicate customization patterns based on existing layout templates by comparing connectivity information to that of existing layout templates and applying applicable structural directives.