The present disclosure presents systems and methods performing a simulation on a hybrid virtual system-on-chip (SoC) model. One such method comprises receiving a configuration file that identifies register transfer level (RTL) abstractions; virtual prototype abstractions; unit-level testbenches; place holder variables; and a shared interface among one or more hardware circuitry blocks designed as RTL abstractions and one or more hardware circuitry blocks designed as virtual prototype abstractions; creating the hybrid virtual SoC model based on the configuration file by instantiating the one or more hardware circuitry blocks designed as RTL abstractions and a stub hardware circuitry block for each of the one or more hardware circuitry blocks designed as virtual prototype abstractions; and integrating unit-level testbenches for the one or more hardware circuitry blocks represented as RTL abstractions.

Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

A method includes obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, where the IP cores include reusable units of logic for a system on a chip (SoC), and performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, where the hierarchical CDC and RDC verification includes consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use in the SoC.

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

Systems and methods generate the design of a tiled multi-core system-on-chip (SoC). Design specification defining a multitude of cores to be used in the tiled multi-core SoC is analyzed and a multitude of subsystems based on the plurality of cores is built. The subsystems are augmented with one or more network adapters to generate the design of the tiled multi-core SoC. To achieve this, a multitude of IP blocks defined by the specification are retrieved from a design library. Design metadata associated with the IP blocks are extracted. Next, a standardized interface is generated for each of the IP blocks using the design metadata. Thereafter, a bus interface is generated for the IP blocks. Next, a tiled synthesizable register-transfer level code for the SoC design is generated in accordance with received configuration information.

A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer, a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.

A system for implementing functional logics of a verification IP using a transaction level modeling (TLM) is provided. The system includes (A) a stimulus generator to initiate a transaction and transmit the transaction through a transaction level model interface, (B) a verification IP unit to receive and process the transaction and (C) a signal-level driver to toggle pins of the design under test (DUT) based on the processed transaction. The verification IP unit is configured to (a) divide functional logics of a verification IP unit into one or more finite state machines (FSMs) when a transaction is received from a stimulus generator, (b) define a set of state variables for each of the one or more FSMs, (c) implement a state class for each state of the one or more FSMs and (d) modify the functionality of the one or more FSMs.

On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.