A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.

Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.

The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect connections resulting from a potential placement at the second position. Embodiments may include determining an influence metric by applying an optimized connectivity rules definition upon the potential placement at the second position and the one or more direct and indirect connections. Embodiments may also include displaying feedback at the graphical user interface based upon, at least in part, the influence metric.

Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.

A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

Methods, machine readable media and systems for simulating the leakage of sensitive data in an integrated circuit, such as cryptographic data or keys, are described. In one embodiment, a method can include the following operations: performing a first dynamic voltage drop (DVD) simulation on a plurality of locations, distributed across an integrated circuit (IC), based on a physical model that specifies physical layout of components on the IC, the IC storing sensitive data in locations of the layout; performing an IC level side channel correlation analysis between each of the locations and the sensitive data based on the results of the first DVD simulation; and selecting, based upon the IC level side channel correlation analysis, a subset of the locations for further simulations to simulate leakage of the sensitive data. Other methods, media and systems are disclosed.