A method includes receiving one or more input Artificial Intelligence (AI) networks, transforming the AI networks into respective graphs including interconnected logical operators, and mapping the graphs onto a design of a hardware accelerator including a plurality interconnected hardware engines. A performance of running the AI networks on the design of the hardware accelerator is simulated using a petri-net simulation.

An extensible processor can include an execution pipeline, one or more extensible control engines and architectural visible control states. The extensible processor can be configured to determine a control state of the one or more extensible control engines from the architectural visible control states. The extensible processor can be further configured to initiate execution of a given one of the extensible control engines when a control state in the architectural visible control states corresponding to the given one of the extensible control engines is enabled, wherein the given one of the extensible control engines comprises control input and control outputs based on one or more control transitions of an instruction. The extensible processor can also be further configured to output a result of execution of the given one of the extensible control engines to the architectural visible control states.

A method for generating instruction sequences for testing a processor design model. The method includes receiving, by an instruction sequence generator (ISG), an initial test template. The initial test template includes an initial set of instruction constraints and a save resumable state command. The ISG generates a first set of executable test instructions based on the initial test template. The ISG initiates the save resumable state command. The ISG creates and saves a snapshot that includes information on a resume state of the ISG and the first set of executable test instructions at the time the save resumable state command is initiated.

A system having design tools and methods for using the same in designing an integrated circuit (IC) are described. In one embodiment, an IC design system, the system comprises one or more processors; and a non-transitory computer readable medium connected to the one or more processors, wherein the non-transitory computer readable medium is configured to store: a first design tool module configured to determine one or more design specifications for a core of an integrated circuit (IC), the IC comprising a plurality of transistors and other components, and a plurality of interconnects between the transistors and the other components, wherein the plurality of transistors and the other components and the plurality of interconnects are formed on a single die, and a second design tool module configured to determine one or more design specifications for a periphery of the IC, the second tool to function independently of the first tool and operable to design constraints for interface placement and configuration of an interface between the core and the periphery of IC.

According to one aspect of the present disclosure a system and method of enhancing random test case generation during pre-silicon design verification of test models of very large scale integration (VLSI) processors and systems is provided. A test sequence including a specification of at least one target state value for at least one resource of the hardware design model is received and includes a state object having at least one state element defining the target state value for a resource. Instructions are generated to transition the at least one resource from an existing state to the at least one target state value. The instructions are executed according to the test sequence to transition the resources to the defined state. State information on the hardware design model is output to allow a process engineer to determine whether the target state value for the resource was successfully changed.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

System and methods are disclosed to qualify networks properties and that can be used for topology synthesis of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metric are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to understand if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wore length used by the network.

A method and a network device for generating a memory access instruction are presented. The method includes obtaining constraints on a memory access instruction, the constraints comprising a target address range and a specification of valid address locations; obtaining simulation state information relating to a current state of a central processing unit (CPU) design simulation; and generating the memory access instruction based on the target address range, the specification of valid address locations, and the simulation state information.

A method for automatic design of a processor and programming and simulation tools, comprising developing a single model of a processor from processor's specifications; providing the single model of the processor to an Electronic Design Automation tool, which automatically generates a hardware description and programming and simulation tools from the single processor model, and automatically determines validity of the single model of the processor, is disclosed. The method further comprises automatic verification of the designed processor.