An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.

The present invention provides a vehicle control device and a vehicle control simulation device that enable, even for parallel processing with a plurality of arithmetic devices, approximation in act between at verification of simulation operation on a model base and at verification of operation on an actual vehicle. Provided are: control model information for control of a system; hardware information for operation of a control model; arithmetic-device allocation information as to which arithmetic device in hardware is allocated to perform arithmetic processing to a control program in the control model; delay time information regarding a case where the control model operates on the hardware; and a delay-time adding unit configured to create delay-inclusive control model information in which the delay time information is inserted in the control model, based on at least either the arithmetic-device allocation information or the hardware information.

Systems and methods are provided for accurately simulating memory operations of a multi-compute-engine system, such as a multi-core system. Simulation speed can be increased by consolidation location and state information associated with data stored in one or more caches of a simulated cache hierarchy. This consolidation of information can be reflected in a single cache line map or flat cache. Accordingly, searches for data (and copies of the data) in each and every cache of the simulated cache hierarchy can be performed fast and with greater efficiency than conventional simulation systems that operate using sequential, cache-by-cache searching, while maintaining data coherency.

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

A method for path routing according to an embodiment of the present disclosure may include selecting a first start point and a first end point with which path routing is performed in a circular frame generated by connecting all points included in one or more start point sets included in a layer, one or more end point sets paired with the start point set, and one or more edge point pair sets to one closed curve, generating a connectivity graph by connecting edge points included in one or more nodes corresponding to segments obtained by dividing the circular frame into one or more regions, and connecting the first start point and the first end point based on a cost for connecting the first start point and the first end point calculated using the connectivity graph.

An infusion pump assembly includes a reservoir assembly configured to contain an infusible fluid. A motor assembly is configured to act upon the reservoir assembly and dispense at least a portion of the infusible fluid contained within the reservoir assembly. Processing logic is configured to control the motor assembly. The processing logic includes a primary microprocessor configured to execute one or more primary applications written in a first computer language; and a safety microprocessor configured to execute one or more safety applications written in a second computer language.

A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.

Systems and methods to translate or convert a desired circuit into a database that instructs a place and route or wire bonding machine where on a substrate to place components and also where to place bond wires on the pads of a connection matrix on a substrate. During the assembly process, the pads of the connection matrix are populated with bond wires using the database.

An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.