Methods, storage mediums, and apparatuses for evaluating the reliability of Three-Dimensional (3D) Network-on-Chip (NoC) designs are described. The described embodiments provide a 3D NoC specific fault-injector tool which is able to model logic-level fault models of 3D NoC specific physical faults in 3D-NoC platform. These embodiments automate the whole process of static and dynamic fault injection base on the user preference and reports the specific reliability metrics for 3D NoC platform as a single tool. The described embodiments can be used for the reliability evaluation and effectiveness of fault-tolerant designs in any of the 3D-many core designs such as manycore systems in different ranges of application from embedded systems in cellphones to larger systems which can be used in next generation of autonomous cars or hypercube memory cells.

A method for adaptive error correction in quantum computing includes executing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In an embodiment, the method includes estimating, responsive to determining an initial state of the quantum processor, a runtime duration for a quantum circuit design corresponding to a quantum algorithm, the quantum processor configured to execute the quantum circuit design. In an embodiment, the method includes computing an error scenario for the quantum circuit design. In an embodiment, the method includes selecting, using the error scenario and the initial state of the quantum processor, a quantum error correction approach for the quantum circuit design. In an embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.

A method for adaptive error correction in quantum computing includes executing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In an embodiment, the method includes estimating, responsive to determining an initial state of the quantum processor, a runtime duration for a quantum circuit design corresponding to a quantum algorithm, the quantum processor configured to execute the quantum circuit design. In an embodiment, the method includes computing an error scenario for the quantum circuit design. In an embodiment, the method includes selecting, using the error scenario and the initial state of the quantum processor, a quantum error correction approach for the quantum circuit design. In an embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.

A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.

A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

A semiconductor package comprises a controlled voltage domain (CVD) and a master voltage domain (MVD). The MVD comprises an error-tolerance control (ETC) circuit. A basic execution block in the CVD generates a basic output value, based on at least two input values. A test execution block in the CVD generates a test digital root, based on digital roots of the input values. A digital root comparator in the CVD determines whether a digital root of the basic output value matches the test digital root. An error reporter in the CVD sends an error report to the ETC circuit in response to a determination that the digital roots do not match. The ETC may automatically adjust at least one power characteristic of the CVD, based on the error report. Other embodiments are described and claimed.

According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.