A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.

The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.

A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if occurred at one or more input ports of the respective sequential element or one or more input ports of a clockgate of the respective sequential element, and identifying a remainder of input ports and input ports of a clockgate of each of the sequential elements at which the faults are not determined to be detectable by the safety mechanism based on the one or a plurality of fault relation rules.

Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.

Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.

Embodiments are provided for providing enhanced protection of an integrated circuit in a computing system by a processor. A logic locking FSM component or a logic locking with RTL gating may be applied to a current design logic to enable and protect operations of an integrated circuit, where the current design logic remains unchanged. The operation of the integrated circuit may be activated based upon providing to the integrated circuit a correct key from the logic locking FSM component or the logic locking with RTL gating.