Systems and methods described in this disclosure relate, generally, to analyzing electronic circuitry, and more specifically, to analyzing efficiency of clock gating in electronic circuitry. Analysis may include identifying wasted propagation of clock signals by clock gates and/or for a circuitry as a whole. In some embodiments, modified gating logic may be determined that improves clock gating efficiency, for example, by eliminating at least some wasted propagation of clock signals.

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

Aspects of the disclosure provide an electronic device. The electronic device can include a first clock gating circuit that is configured to receive a clock signal and selectively transmit a clock pulse of the clock signal when triggered, access circuitry configured to launch configuration data in response to receiving a write request from a management module and trigger the first clock gating circuit to generate a first clock pulse that is delayed by a first predetermined amount of time after the launch of the configuration data by the access circuitry, and a first memory element configured to capture the configuration data in response to receiving the delayed first clock pulse generated by the first clock gating circuit.

The independent claims of this patent signify a concise description of embodiments. Multiple copies of the design or multiple designs are compiled into a single emulation module or prototype FPGA/sub-system to enable multiple concurrent users. The design is executed on the emulator or prototype with the main design clock always running. A debug transactor is attached to each copy of the design which connects to one software debugger per user. The improvement is especially important for long interactive debug sessions which often occur with embedded-software debug use models. This Abstract is not intended to limit the scope of the claims.

A layout method of a semiconductor device is disposed. The layout method includes: disposing a first metal strip directed to a first clock signal and disposing a first block strip parallel with the first metal strip, wherein the first block strip is indicative of a first blockage which prevents a routing tool from placing another metal strip on the location of the first block strip.

Methods, systems and computer program products for improved placement of a clock gating latch are provided. Aspects include identifying a clock gating latch that is designated to control a local clock buffer. Aspects also include determining a plurality of data latches that are designated to be controlled by the local clock buffer. Aspects also include determining positions of the plurality of data latches within a layout. Aspects also include determining a position of the clock gating latch within the layout based on the positions of the plurality of data latches within the layout.

Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

Methods, systems and computer program products for improved placement of a clock gating latch are provided. Aspects include identifying a clock gating latch that is designated to control a local clock buffer. Aspects also include determining a plurality of data latches that are designated to be controlled by the local clock buffer. Aspects also include determining positions of the plurality of data latches within a layout. Aspects also include determining a position of the clock gating latch within the layout based on the positions of the plurality of data latches within the layout.

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.