Embodiments herein describe reconfigurable integrated circuits (ICs) which include programmable logic that can be configured to perform a user task. In one embodiment, the programmable logic is configured as an accelerator. The user may want to gather debug data or profiling data when executing the accelerator. Rather than using debug/profile circuitry disposed in a static region of the IC, the user can provide preferences to a linker which then dynamically configures debug/profile circuitry in a dynamic region of the IC. That is, based on user preferences, the linker can generate customized debug/profile circuitry for monitoring the performance of the accelerator. In one embodiment, the debug/profile circuitry is implemented in the dynamic region of the IC and is tailored to user preferences rather than relying on static, or fixed, debug/profile circuitry. Moreover, the user can retrieve the debug/profiling data on demand using a call back and a device driver.

A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

The present disclosure relates to testing structures and, more particularly, to a circuit and method for design of RF integrated circuits for process control monitoring. The circuit includes a radio frequency integrated circuit comprising a plurality of active NFET devices and passive devices arranged in a single topography; and a plurality of NFET switches which are configurable to diagnose physical failures of the plurality of active NFET devices and the passive devices by isolating selected ones of the plurality of active NFET devices and the passive devices into different built-in circuit topologies by selectively turning on and off the plurality of active NFET devices and the passive devices.

This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, and generate code coverage bins based on the operational states of the circuitry. The operational states of the circuitry correspond to operational capabilities of the circuitry supported by each of the power modes for the circuitry. The code coverage bins are configured to store code coverage events occurring when the circuitry operates in different power modes. The design verification tool can utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment, and also can generate at least one coverage metric based on the records of the code coverage events.

Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.

Systems and methods of restraining reverse engineering process for analog integrated circuit use techniques of adding dummy devices, device fragmentation, increasing bus width, employing different layouts for the same circuit element and mixing different types of passive devices increase complexity and makes the layout floorplan more difficult to be extracted for the reverse engineering. The system adds dummy devices and ensures the extra devices and capacitance do not affect the target circuit performance.

A programmable integrated circuit includes rows of circuit blocks and up and down driving vertical interconnect resources. Each of the up and down driving vertical interconnect resources comprises a programmable signal path coupled to at least two of the rows of circuit blocks. A defect in any one of the up driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in the up driving vertical interconnect resources that originate in different ones of the rows of circuit blocks. A defect in any one of the down driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in the down driving vertical interconnect resources that originate in different ones of the rows of circuit blocks.

An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.