The present disclosure describes system and methods for network planning. The systems and methods can incorporate network traffic demands, availability requirements, latency, physical infrastructure and networking device capability, and detailed cost structures to calculate a network design with minimum or reduced cost compared to conventional methods. In some implementations, the method include providing an initial, deterministic set of failures, and then successively performing a network optimization and a network availability simulation to determine which failures most impact the performance of the network model. The high impact failures can then be provided back into the system, which generates an improved network design while still maintaining minimum cost.

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.

Improving reliability of an electronic device includes: determining whether a side space of an interconnect of the electronic device is available for a redundant interconnect, determining whether a line end electrically coupled to the interconnect may be extended into the side space for a distance sufficient to accommodate a redundant interconnect, extending the line end into the side space for the distance when available, and adding the redundant interconnect electrically coupled to the extended line end.

Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

The present disclosure describes system and methods for network planning. The systems and methods can incorporate network traffic demands, availability requirements, latency, physical infrastructure and networking device capability, and detailed cost structures to calculate a network design with minimum or reduced cost compared to conventional methods. In some implementations, the method include providing an initial, deterministic set of failures, and then successively performing a network optimization and a network availability simulation to determine which failures most impact the performance of the network model. The high impact failures can then be provided back into the system, which generates an improved network design while still maintaining minimum cost.

Out-of-bounds recovery circuits are configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.