A pre-step co-simulation method and device for co-simulation of several subsystems is disclosed, utilizing partial derivatives of replacement subsystems. On this basis, the exact solutions of output variables of the individual subsystems are approximated by evaluation of an Error Differential Equation in order to estimate the future progress of the approximated exact output variables; corresponding input variables are determined by optimization prior to the current co-simulation time increment. The pre-step co-simulation method is realized within a computer-executable program and implemented in a network of computing nodes.

An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay and a processor coupled to the programmable circuitry. The processor can be configured to control the programmable circuitry through execution of a framework. The framework provides high-productivity language control of implementation of the overlay in the programmable circuitry.

A programmable operation and control chip, comprising: at least one controller with a control flow operation mode; at least one bus; at least one programmable operation structure with data stream flow operation mode which communicates with the controller via the bus and the data buffering structure to control and schedule the programmable operation structure and/or the data buffering structure, and allocate and process serial and parallel operation of data and/or dynamically reconfigure internal structure of the chip.

Methods and systems to model, simulate and continuously analyze global non-functional properties, such as profitability, availability, security and performance, of complex Internet of Things (IoT) systems. This modeling enables the collaborative design, interoperability, documentation, simulation, testing, deployment, operations, analysis and optimization of connected services and IoT infrastructures. Various embodiments of the present invention may be characterized as a tool for modeling an IoT system and controlling the evolution of this system. The present invention enables a customer or any entity to describe and simulate an IoT system in different scenarios and, in turn, derive various estimates for what the customer will have to invest. This is of great benefit to entities since building out and implementing a complex IoT system is likely an expensive and time and resource consuming endeavor.

Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.

Methods and apparatus for implementing a programmable integrated circuit using circuit design tools are provided. The circuit design tools may receive a high-level synthesis source code, parse the high-level synthesis source code to generate a compiler intermediate representation, process the compiler intermediate representation to generate a register transfer level (RTL) description, and then synthesize and compile the RTL description to generate an output netlist. Timing analysis may be performed on the output netlist to identify a critical path. Components in the critical path may be mapped back to specific portions in the RTL descriptions, to specification portions of the compiler intermediate representation, and to specific lines in the high-level synthesis source code. The designer can then optimize the high-level synthesis source code to shorten the critical path. This process may be iterated as many times as desired.

Systems and methods for designing a robotic system architecture are disclosed. The methods include defining a software graph including a first plurality of nodes, and a first plurality of edges representative of data flow between the first plurality of tasks, and defining a hardware graph including a second plurality of nodes, and a second plurality of edges. The methods may include mapping the software graph to the hardware graph, modeling a latency associated with a computational path included in the software graph for the mapping between the software graph and the hardware graph, allocating a plurality of computational tasks in the computational path to a plurality of the hardware components to yield a robotic system architecture using the latency, and using the robotic system architecture to configure the robotic device to be capable of performing functions corresponding to the software graph.

Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are reordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.

A method of simulating codes that form a program configured to control a control target includes causing a processor to execute the following: first-setting a first process of executing a simulation of an operation of a code group excluding a specific code among the codes; second-setting a second process of executing a simulation of an operation of a specific model obtained by modeling the specific code; first-simulating, in the first process, a first simulation of a code preceding the specific code in the code group; second-simulating, in the second process, a second simulation of the specific model through use of an execution result of the first simulation by inter-process communication between the first process and the second process; and third-simulating, in the first process, a third simulation of a code succeeding the specific code through use of an execution result of the second simulation by the inter-process communication.

Example implementations involve systems and methods which can involve storing interface (I/F) communication activity records of a plurality of simulation engines during execution of a co-simulation, and for a subsequent execution of the co-simulation, replacing one or more of the plurality of simulation engines with a simulation engine repeater configured to reproduce I/F communication activity from the stored I/F communication activity records corresponding to the replaced one or more of the plurality of simulation engines during the subsequent execution of the co-simulation and to log a real time consumed for execution of the reproduced I/F communication activity in the subsequent execution and a simulation time consumed for execution of the reproduced I/F communication activity for each simulation step, the real time determined based on a real time difference between a start of each simulation step and completion of synchronization with a co-simulator bus at an end of each simulation step.