This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes. The management process can determine to have the participating processes synchronously transition to another one of the phases or that the participating processes have compiled the circuit design into a compiled design corresponding to the circuit design, and deploy the compiled design in an emulator for verification of a functionality of the electronic device.

Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.

Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.

A software studying unit (122) calculates software processing time of each of a plurality of functions in a target source program. A data-flow graph generation unit (121) generates an inter-function data-flow graph of the plurality of functions based on the target source program. A hardware studying unit (130) calculates hardware processing time of each function and a circuit scale of each function by a high-level synthesis for the target source program. An implementation combination selection unit (140) selects, based on the software processing time of each function, the hardware processing time of each function, the circuit scale of each function, and the inter-function data-flow graph, an implementation combination of one or more functions to be implemented by software and one or more functions to be implemented by hardware.

In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and computing entities for modifying a design of a hardware IP. According to one embodiment, a method is provided, the method including generating a control and data flow graph (CDFG) representation for portions of the design. The method further includes partitioning the CDFG representation into a set of partitioned sub-graphs. The method further includes, for each partitioned sub-graph, generating a merged sub-graph to form a set of merged sub-graphs. Generating the merged sub-graph for each partitioned sub-graph involves generating a container sub-graph and merging the container sub-graph with the partitioned sub-graph to form the merged sub-graph. The container sub-graph may be a modification of the partitioned sub-graph with respect to an identified feature, in some examples. The method further includes synthesizing a modified design of the hardware IP including the set of merged sub-graphs.

Systems and methods for designing a robotic system architecture are disclosed. The methods include generating a model that defines one or more requirements for a robotic device for a mapping between a software graph and a hardware graph. The model is used for allocating a plurality of computational tasks in a computational path included in the software graph to a plurality of hardware components of the robotic device to yield a robotic system architecture. The methods also include using the robotic system architecture to configure the robotic device to be capable of performing functions corresponding to the software graph, where the robotic system architecture is optimized to meet one or more latency requirements.

Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.

Methods and apparatus relating to heterogeneous compute architecture hardware/software co-design for autonomous driving are described. In one embodiment, a heterogeneous compute architecture for autonomous driving systems (also interchangeably referred to herein as Heterogeneous Compute Architecture or “HCA” for short) integrates scalable heterogeneous processors, flexible networking, benchmarking tools, etc. to enable (e.g., system-level) designers to perform hardware and software co-design. With HCA system engineers can rapidly architect, benchmark, and/or evolve vehicle system architectures for autonomous driving. Other embodiments are also disclosed and claimed.

A hybrid emulation system includes a hardware emulation system, a simulation system, and a co-simulation interface. The hardware emulation system emulates a first portion of a design under test (DUT) during a hybrid emulation. The emulation runs in a first time domain local to the hardware emulation system. The simulation system simulates a second portion of the DUT during the hybrid emulation. The simulation runs in a second time domain local to the simulation system. The first time domain and the second time domain are unsynchronized. The co-simulation interface is coupled to the simulation system and the hardware emulation system. The co-simulation interface communicates transactions and events between the hardware emulation system and the simulation system. For each transaction, the co-simulation interface captures a transaction time in the first time domain, and for each event, the co-simulation interface captures an event time in the first time domain.

Model-based implementation of a design for a heterogeneous integrated circuit can include converting a model, created as a data structure using a modeling system, into a data flow graph, wherein the model represents a design for implementation in an integrated circuit having a plurality of systems, the systems being heterogeneous, classifying nodes of the data flow graph for implementation in different ones of the plurality of systems of the integrated circuit, and partitioning the data flow graph into a plurality of sub-graphs based on the classifying, wherein each sub-graph corresponds to a different one of the plurality of systems. From each sub-graph, a portion of high-level language (HLL) program code can be generated. Each portion of HLL program code may be specific to the system corresponding to the sub-graph from which the portion of HLL program code was generated.