Systems and method for performing an XiL-based simulation are provided. Operating data sets (BDS) are read, An artificial intelligence system is trained with the operating data sets (BDS) Test data sets (TDS) are generated using the trained artificial intelligence system. The test data sets (TDS) are provided for the XiL simulation.

This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes. The management process can determine to have the participating processes synchronously transition to another one of the phases or that the participating processes have compiled the circuit design into a compiled design corresponding to the circuit design, and deploy the compiled design in an emulator for verification of a functionality of the electronic device.

Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.

Methods and apparatus relating to heterogeneous compute architecture hardware/software co-design for autonomous driving are described. In one embodiment, a heterogeneous compute architecture for autonomous driving systems (also interchangeably referred to herein as Heterogeneous Compute Architecture or “HCA” for short) integrates scalable heterogeneous processors, flexible networking, benchmarking tools, etc. to enable (e.g., system-level) designers to perform hardware and software co-design. With HCA system engineers can rapidly architect, benchmark, and/or evolve vehicle system architectures for autonomous driving. Other embodiments are also disclosed and claimed.

Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.

In a simulation device (100), a calculation section (113) calculates an execution processing time required for executing each instruction code (221) of a plurality of instruction codes. A storage section (140) stores change setting information (230) in which a change rule that changes execution processing times of the plurality of instruction codes included in the processing unit is set. A change section (115) changes the execution processing time into a changed processing time according to the change rule being set in the change setting information (230). The change section (115) also includes the changed processing time of each instruction code of the plurality of instruction codes, in an entire time point (240). A simulation execution section (116) executes a simulation of a target program (210) using the entire time point (240). A monitoring section (120) monitors a status of a target model during execution of the simulation.

A programming language and a compiler are disclosed that optimize the use of look-up tables (LUTs) on a synchronous digital circuit (SDC) such as a field programmable gate array (FPGA) that has been programmed. LUTs are optimized by merging multiple computational operations into the same LUT. A compiler parses source code into an intermediate representation (IR). Each node of the IR that represents an operator (e.g. ‘&’, ‘+’) is mapped to a LUT that implements that operator. The compiler iteratively traverses the IR, merging adjacent LUTs into a LUT that performs both operations and performing input removal optimizations. Additional operators may be merged into a merged LUT until all the LUT's inputs are assigned. Pipeline stages are then generated based on merged LUTs, and an SDC is programmed based on the pipeline and the merged LUT.

The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

A system for manufacturing, testing, integrating, and operating of live or virtual platforms and components thereof uses a simulation engine and/or a testbed engine in a live-virtual-constructive (LVC) environment. The system can be used in a pure simulated environment or for testing of individual subsystems on a live platform (e.g., a live aircraft) with remaining subsystems in simulation, to incremental integration of all subsystems onto live aircraft.

A method for testing platforms (e.g., live, virtual, and/or constructive platforms associated with autonomous aircraft systems and their component subsystems) in a live/virtual/constructive (LVC) environment. In embodiments, the method includes determining, via a testbed engine, the development state of a platform component under test. The method includes retrieving a test to be executed, the test including test conditions to be applied to the component. The method includes determining whether the component is enabled to respond to the test conditions. The method includes, if the component is enabled to respond to the test conditions, executing the test while monitoring the component to detect a first output response and a second output response. The method includes identifying, via the testbed engine, at least one change in the development state of the component by comparing the first and second output responses.