In a processing unit, a processor core executes instructions in a plurality of simultaneous hardware threads, where multiple of the plurality of hardware threads concurrently execute memory transactions. A transactional memory circuit in the processing unit tracks transaction footprints of the memory transactions of the multiple hardware thread. In response to detecting failure of a given memory transaction of one of the plurality of multiple threads due to an overflow condition, the transactional memory circuit transitions to a throttled operating mode and reduces a number of hardware threads permitted to concurrently execute memory transactions.

Simulation of execution of a processing workload by a target hardware device is provided by providing workload data specifying the processing workload, passing the workload data to both a primary partial simulation and a complementary partial simulation that run in parallel and acquire input data from different levels of abstraction of the target hardware and then simulating execution of the processing workload using a primary partial simulation to generate primary partial result state data and using the complementary partial simulation to generate complementary partial result state data. The target hardware device may be a graphics processing unit and the workload data may specify the processing to be performed in a hardware independent form, such as, for example, OpenGL ES. The host system supporting the simulation may include a graphics processing unit serving to provide the complementary partial simulation due to its own execution of the workload data.

Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a file. A database of register and memory values which represent the complete history of register and memory value changes during a simulation can be created from trace information and can be accessed to non-intrusively obtain any processor register or memory value during simulation. The processor register and memory values of the database can also be accessed to symbolically show the behavior of ESW concurrently with hardware behavior in the simulation.

Disclosed are a multi-dimensional segmentation method and apparatus for a 5G-oriented protocol stack, and a terminal. The method comprises: segmenting an MAC layer in a protocol stack, and putting HARQ entities of a physical layer and the MAC layer together in a pre-set physical resource for processing; and moving a relevant partial module of the physical layer to an FPGA for processing according to a calculation amount and functional requirements. The hardware configuration requirements are reduced on the basis of guaranteeing the performance.

An apparatus to implement functional safety control logic (FSCL) in an autonomous driving system comprises a field-programmable gate array (FPGA) comprising logic elements to be partitioned into a first section to implement one or more safety cores and a second section to implement one or more non-safety cores, a memory to couple to the safety core or to the non-safety core, and a trusted execution environment (TEE) to couple to a remote administrator via a network and to apply a configuration received from the remote administrator to the FPGA. The safety core is to function as an active agent for FSCL during operation, and the non-safety core is to function as a failover agent during operation, and wherein the non-safety core is to perform a liveliness check on the safety core to monitor for a failover and to take over as the active agent in the event of a failover.

A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.

An accelerator image generator includes a synthesis block and a simulation block. The accelerator image generator receives a hardware description language representation for a desired function, inputs the hardware description language representation for the desired function to the synthesis block and to the simulation block so the synthesis block and simulation block work in parallel, monitors progress of the synthesis block and the simulation block, and when a defined threshold is reached in the synthesis block, halts the simulation block while the synthesis block continues until the synthesis block outputs an accelerator image for deployment to a programmable device. When an error is detected in the synthesis block following halting of the simulation block, the simulation block may be resumed, and the defined threshold may be adjusted. The accelerator image can be deployed to a programmable device to provide a hardware accelerator corresponding to the accelerator image.

A method for simulating operation of a system. The method accesses information characterizes system behavior, identifies system components and characterizes component behavior and relationships. The components include composite or non-composite unit types. A user selects an instance root and the method induces an instance hierarchy from that root. The instance hierarchy is displayed on a GUI in the form of a navigable tree or breadcrumbs view. Operation of the system is simulated using the instance hierarchy. Embodiments further include the concepts of merging certain variable names, displaying producing and consuming downstream and upstream elements, positioning, rotating, or orienting diagram elements to avoid overlapping with other diagram elements, identifying statically constant variables and propagating constness to producer and consumer variables, storing simulation results in compressed form and decompressing as needed, and identifying differences between dataflow diagrams.

In a simulation device (100), a calculation section (113) calculates an execution processing time required for executing each instruction code (221) of a plurality of instruction codes. A storage section (140) stores change setting information (230) in which a change rule that changes execution processing times of the plurality of instruction codes included in the processing unit is set. A change section (115) changes the execution processing time into a changed processing time according to the change rule being set in the change setting information (230). The change section (115) also includes the changed processing time of each instruction code of the plurality of instruction codes, in an entire time point (240). A simulation execution section (116) executes a simulation of a target program (210) using the entire time point (240). A monitoring section (120) monitors a status of a target model during execution of the simulation.