The present disclosure provides a semiconductor device. The semiconductor device includes: a first cell, a dielectric layer, and a snorkel structure. The first cell has an output terminal. The dielectric layer is disposed on the first cell. The snorkel structure is disposed in the dielectric layer. The snorkel structure includes a first conductive structure, a first conductive layer, and a second conductive structure. The first conductive layer is electrically connected to the output terminal of the cell. The first conductive layer is disposed on and electrically connected to the first conductive structure. The second conductive structure is disposed on and electrically connected to the first conductive layer. The second conductive structure has a topmost conductive layer buried in the dielectric layer.

Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.

Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.

A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k*σ.sub.max; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.

Examples described herein provide for a technique for metal track routing with buffer bank insertion in a representation of a hardware design of an integrated circuit. In an example, pins of ports of hardblocks in a placed layout are identified. Logical tracks for nets associated with the pins of the ports are generated and assigned to respective metal layers. Logical tracks and corresponding nets are grouped into respective groups. Buffer bank(s) is inserted into the placed layout. Each buffer bank is for a group of logical tracks and divides each logical track and net of the group of logical tracks. Each buffer bank has pins associated with the respective divided nets. Each pin of the buffer bank(s) is assigned to a middle or higher metal layer. Metal tracks are generated in a representation of a hardware layout based on the logical tracks and pins of the ports and buffer bank(s).

A computer/software tool for electronic design automation (EDA) uses parasitic elements from a post-layout netlist (PLN) file for a given IC design to assess routing-imposed RC-based signal degeneration. The computer/software tool facilitates selection of, and insertion location for, one or more “virtual repeaters,” based on modification to the PLN file. The tool generates a visual display based on the calculated design characteristics, facilitating adjustment and optimization of repeater cell and location by the designer. The repeater insertion is “virtual,” because modeling and adjustment can be based on abstractions (e.g., load capacitance presented by a repeater) and the already-extracted netlist file, and because an actual circuit design need not be created until after a designer has fine-tuned repeater insertion parameters.

A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include creating a plurality of library (lib) cells for a directional routing layer, and determining a lib cell of the plurality of lib cells for placement of at least one repeater for the directional routing layer. The operations may also include determining a route touch region corresponding to a pin region of the lib cell through which a route is going through and inserting the at least one repeater at the route touch region. The operations may also include swapping the at least one inserted repeater to at least one target lib cell of the plurality of lib cells.

Route segments of a set of nets may be grouped into route groups. Terminals of the set of nets may be grouped into terminal groups. For each net in the set of nets, a net signature may be determined based on route groups associated with the net and terminal groups associated with the net. The set of nets may be grouped into net groups based on the net signatures.