A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.

A layout design support apparatus 100 determines, in a circuit element connected to a first external terminal P1 to which a first potential identification label is added, whether to short-circuit one terminal connected to the first external terminal P1 and another terminal based on a determination criterion according to element type information and breakdown voltage information, adds the first potential identification label to the circuit components on a path from the first external terminal P1 to the one terminal of the circuit element to identify a first equipotential region according to determining not to short-circuit, repeatedly performs determination for the circuit element connected to the another terminal and identifies the first equipotential region according to determining to short-circuit, and identifies a second equipotential region when receiving a second potential identification label to be added to a second external terminal P2.

A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration: selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.

A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.

A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern thereby revising the layout diagram.

A method of generating an IC layout diagram includes positioning a cell in the IC layout diagram relative to a first metal layer cut region alignment pattern and overlapping the cell with a first metal layer cut region. The cell includes a first metal layer region corresponding to one of a first or second mask set, the first metal layer cut region alignment pattern includes a sub-pattern corresponding to the one of the first or second mask set, and the first metal layer cut region corresponds to the sub-pattern.

A system and method for adjusting the shapes of polygons in a design. In some embodiments, the method includes inverting a first layer of the design, the first layer comprising one or more polygons, the inverting of the first layer forming a region complementary to the union of the polygons of the first layer, and including one or more inverse polygons. The method may further include performing a rounding operation on a first corner of a first inverse polygon of the one or more inverse polygons, to form a modified polygon.

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

Split stack triple height cells and methods of generating layouts of same are described herein. The structure includes a circuit formed within three stacked rows. The circuit includes a first stage having a first plurality of electrical components and a second stage having a second plurality of electrical components. The first row includes a first electrical component of the first plurality of electrical components within a top portion of the first row. A first electrical component of the second plurality of electrical components is within a bottom portion of the first row and a top portion of the second row. A second electrical component of the second plurality of electrical components is within a top portion of the third row and a bottom portion of the second row. A second electrical component of the first plurality of electrical components is within a bottom portion of the third row.

A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram.