A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

A non-transitory computer-readable storage medium storing a prediction program that causes at least one computer to execute a process, the process includes simulating a flow of people based on a plurality of behavior intentions of people; evaluating the simulated flow based on observation data of the flow of people; and predicting the flow of people based on an evaluation result of the simulated flow of people.

Computer-implemented systems and methods for automatically eliminating connectivity mismatches in a mask layout block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints. Disclosed systems and methods analyze a physical connection of a selected polygon or net in a mask layout block and obtain connectivity information associated with the selected polygon or net from a netlist or external constraints file. The physical connection of the selected polygon or net is compared with the obtained connectivity information to determine whether there is a connectivity mismatch associated with the selected polygon or net. If there is a determined connectivity mismatch, a violation marker representing the connectivity mismatch is generated and the connectivity mismatch is corrected by placing, moving, or editing the selected polygon or net to modify the physical connection.

A computer-implemented method for computationally determining ventilation efficiency when generating a building design comprises: generating a first three-dimensional (3D) mesh based on a first 3D building model; performing a first fluid dynamic computer simulation based on the first 3D mesh and first environmental data associated with the first 3D building model to generate a first output data set; and computing, based on the first output data set, a first value for a ventilation performance metric that is associated with the first 3D building model.

A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.

Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.

Determining coordinates and an initial coordinate system of simulation points according to structural drawings, and transforming the coordinate system so that Y axis is parallel to the wind direction, to obtain a 3D model of N structural simulation points; projecting all the simulation points of the 3D model onto a target 2D plane, and transforming the simulation points into projection points on the 2D plane; calculating the delay time of the wind speed, that is, the time required to move from each point to the projection points on the target plane; using a 2D coherence function to consider the spatial correlation of different simulation points in horizontal and vertical directions; generating fluctuating wind speed by using harmony superposition method; and obtaining the wind speed time history of all the points by using the delay time.

Systems and methods for semi-discrete modeling of progressive damage and failure in composite laminate materials are disclosed. An example method includes receiving, from a user, a fibrous strip width and a fibrous strip spacing, and creating a finite-element (FE) mesh by: generating, using a structured hex meshing algorithm, a plurality of fibrous strips along a fiber direction based on the fibrous strip width and the fibrous strip spacing, and generating, using a free hex-dominated advancing front meshing algorithm, a bulk element between each of the plurality of fibrous strips. The FE mesh may define a portion of a composite laminate material. The example method includes determining a predicted mechanical response of the composite laminate material by: generating a constitutive model corresponding to the composite laminate material based on the FE mesh, and inputting a stress value or a strain value to the constitutive model to generate the predicted mechanical response.

There is provided systems and methods to determine a first identifier for first product and manufacturing information (PMI); determine a first computer-aided design (CAD) model comprising a plurality of features; associate a first feature of the plurality of features with the first identifier, wherein the first feature is identified by a second identifier;

associate validation data for the first PMI with the second identifier; detect selection of the first feature in the CAD model; and in response to the detected selection, provide a graphical indication of the validation data.

A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs. as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.