Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.

Discussed herein are devices, systems, and methods for determining whether to conduct a mission. A method can include partitioning, by processing circuitry configured to implement a model for determining a value representing a probability that operation of an electronic part of a device will be upset by a single event effect (SEE), a trajectory of the device into disjoint time segments. The method can include determining, based on an effective shielding of the device and one or more flux lookup tables (LUTs) for each of the time segments, respective SEE rates experienced by the electronic part for each time segment. The method can include determining, based on the determined respective SEE rates and using the model, the probability. The method can include permitting the device to traverse the trajectory only if the determined probability is less than a specified threshold.

A pipe diagnosis apparatus 10 includes a simulation execution unit 11 that simulates vibrations of pressure in a pipe included in piping equipment to be diagnosed, based on pipe information for specifying a configuration of the piping equipment, and a stress analysis unit 12 that calculates stress that occurs in a pipe included in the piping equipment, based on pressure vibrations acquired through simulation.

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.

A method for determining fault types in a circuit design includes obtaining circuit elements, a first observation point of a first circuit element, and a first diagnostic point of a first safety circuit device. The method further includes determining a first cone of influence including a first subset of the circuit elements based on the first observation point. The first subset of the circuit elements includes the first circuit element. Further, the method includes determining a first safety cone including a second subset of the circuit elements based on the first diagnostic point. The first safety cone includes the first safety circuit device. The method further includes determining a fault type associated with the circuit elements based on an intersection between the first cone of influence and the first safety cone.

A safety analysis method is based on a safety-specific design structural analysis and cone of influence (COI) that does not require fault simulation. The method for performing a safety analysis of an integrated circuit based on a safety-specific design structural analysis and cone of influence comprises generating with a processor a computed set of basic design elements by intersecting two transitive cones of influence, wherein a first cone of influence is a transitive fanin cone of influence starting from a TO element and a second cone of influence is a transitive fanout cone of influence starting from a FROM element.

Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.

An information processing apparatus has an output data acquisition unit configured to acquire an output value obtained by performing an experiment or simulation based on an input parameter of a predetermined number of dimensions, an evaluation value calculation unit configured to calculate and output an evaluation value of the output value, an outlier processing unit configured to output a converted evaluation value including a specified value obtained by converting the evaluation value that does not satisfy a predetermined criterion, a next input parameter determination unit configured to determine a next input parameter based on the input parameter and the converted evaluation value corresponding to the input parameter, and an iteration determination unit configured to repeat processing of the output data acquisition unit, the evaluation value calculation unit, the outlier processing unit, and the next input parameter determination unit until a predetermined condition is satisfied.

A programmable operation and control chip, comprising: at least one controller with a control flow operation mode; at least one bus; at least one programmable operation structure with data stream flow operation mode which communicates with the controller via the bus and the data buffering structure to control and schedule the programmable operation structure and/or the data buffering structure, and allocate and process serial and parallel operation of data and/or dynamically reconfigure internal structure of the chip.

An information processing apparatus includes one or more memories; and one or more processors coupled to the one or more memories and the one or more processors configured to decompose a first matrix of a coupling coefficient which represents interaction between a plurality of variables into a plurality of matrices by using a rank number, obtain, from the plurality of matrices, a second element that corresponds to a first element of the coupling coefficient, and restore the first element based on the second element.