A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.

Disclosed are example embodiments of a system for providing remote management of asset and protection relays, including a memory and a processor, coupled to the memory. The processor is configured to execute instructions from the memory causing the processor to addresses data management, personnel training, systems integration, maintenance testing, documentation combined with change management workflows.

Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.

Example implementations involve systems and methods which can involve storing interface (I/F) communication activity records of a plurality of simulation engines during execution of a co-simulation, and for a subsequent execution of the co-simulation, replacing one or more of the plurality of simulation engines with a simulation engine repeater configured to reproduce I/F communication activity from the stored I/F communication activity records corresponding to the replaced one or more of the plurality of simulation engines during the subsequent execution of the co-simulation and to log a real time consumed for execution of the reproduced I/F communication activity in the subsequent execution and a simulation time consumed for execution of the reproduced I/F communication activity for each simulation step, the real time determined based on a real time difference between a start of each simulation step and completion of synchronization with a co-simulator bus at an end of each simulation step.

Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

In order to expedite testing (such as silicon chip testing), a test pattern that indicates a timing, order, and frequency (e.g., speed) of signals sent during the test may be divided into different portions. Also, a frequency at which each portion of the test pattern is to be run is determined. Each portion is run at a frequency that can be supported by only that portion. As a result, the slowest portion of the test pattern only limits the frequency at which its portion is run, while other portions are run at a faster frequency. This reduces a time taken to run the test pattern in a testing environment.

A method for automatically interpreting a piping diagram comprising objects, wherein at least two objects are each linked with operational requirements, an operational requirement is defined based on a predefined set of operating principles and based on a predefined set of boundary conditions, the operational requirements included in the piping diagram are successively evaluated during the automatic interpretation, an automation function is generated for an operational requirement and at least based on an operating principle that is included as an intended purpose in the operational requirement, and the automation function is connected to the objects linked via the underlying operational requirement.

A method for designing a borehole tubular for use in a borehole. The method may include defining tubular sections that make up the borehole tubular, defining a downhole operation that will be conducted using the borehole tubular at a first timestamp, determining loads that will be applied to each of the tubular sections at respective specific depths along the borehole during the downhole operation at the first timestamp, determining a design limit envelope for each of the tubular sections at the first timestamp based on design parameters of the tubular section and the specific depth of the tubular section at the first timestamp, and displaying a three-dimensional (3D) plot of the design limit envelopes of the tubular sections and the loads applied to the tubular sections as a function of depth within the borehole on a display.

A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a dominant feature among a plurality of features of the plurality of paths. The dominant features of the plurality of groups are different from each other. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

A computer-implemented method for validating simulation data of a simulation model of a technical system. The method includes the following steps: providing a number n of simulation signals for a number N of QOIs (Quantities of Interest), of the simulation model and providing a number m of reference signals for a number N of QOIs of a reference corresponding to the QOIs of the simulation model; determining a particular metric for the N QOIs, determining an overall metric based on the N metrics, at least one metric of the N metrics being taken into consideration in weighted form in the overall metric using a respective weighting coefficient, and determining an overall difference between the n simulation signals and m reference signals, using the Wasserstein metric based on the overall metric.