A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

In a method for simulation of operation/component states of a plant, process data of the plant components are measured and recorded, including associated uncertainties of the process data. Subsequently, the process data including the associated uncertainties are subjected to a validation to produce validated process data. Based on the validated process data, component characteristics with uncertainty values in accordance with the validated process data are determined. The method can be used in a power plant.

A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.

An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.

A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.

The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

The design assistance device includes: an acquisition unit configured to acquire system information indicating a configuration of the DC bus of the DC power supply system; and an output unit configured to output information on stability of the DC power supply system based on the system information acquired by the acquisition unit and a current value required for each operation of the one or more servo devices. With this configuration, it is possible to analyze the stability of a DC power supply system in which power is supplied from a DC power supply to one or more servo devices including an inverter circuit and an electric motor by a DC bus, in consideration of the configuration of the DC bus.

A computer-implemented method for vehicle impact analysis including obtaining a B-Rep representing an outer surface of a vehicle, the B-Rep having faces and obtaining a radius value for a contact sphere. The method also includes determining one or more two-point-contact curves of the B-Rep for the radius value. The determining includes, for each respective two-point-contact curve, solving a respective differential equation based on the B-Rep. The method forms an improved solution for vehicle impact analysis.

Systems and methods of generating a threat model from a code file are defined. The system includes one or more data stores communicatively coupled with a processor, and storing information on a plurality of properties to be configured for one or more resources included in the code file and a plurality of security threats associated with one or more values of the plurality of properties. The system analyzes the code file to identify one or more properties associated with the one or more resources included in the code file. For each property, a value for the property defined in the code file is identified, one or more security threats are determined based on the identified value for the property, using the information stored in the data stores. The system generates a threat model for the one or more resources based on the determined one or more security threats.

A computer executable system that runs symbolic simulation with formal X-analysis along with logic simulation to determine if Xs produced in logic simulation are real or not. Simulated values in logic simulation shown to be incorrect are rectified using formal analysis results to produce X-accurate simulation results that match real hardware.