Computer-implemented systems and methods for automatically eliminating connectivity mismatches in a mask layout block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints. Disclosed systems and methods analyze a physical connection of a selected polygon or net in a mask layout block and obtain connectivity information associated with the selected polygon or net from a netlist or external constraints file. The physical connection of the selected polygon or net is compared with the obtained connectivity information to determine whether there is a connectivity mismatch associated with the selected polygon or net. If there is a determined connectivity mismatch, a violation marker representing the connectivity mismatch is generated and the connectivity mismatch is corrected by placing, moving, or editing the selected polygon or net to modify the physical connection.

A memory device includes at least one bit line, at least one word line, and at least one memory cell comprising a capacitor and a transistor. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The insulating material is configured to break down under a predetermined break-down voltage or higher applied between the first end and the second end.

A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.

Implementations are directed to methods, systems, and computer-readable media for data hazard generation for instruction sequence generation. In one aspect, a computer-implemented method includes: obtaining data hazard information defining a data hazard to be generated during computer instruction generation, the data hazard specifying a data dependency between a first instruction and a second instruction occurring after the first instruction, and generating, based on the data hazard information and register usage data of a plurality of registers, an instruction for execution in a current processing cycle that satisfies the data dependency specified by the data hazard. The register usage data specifies, for each register of the plurality of registers, whether data was read from or written into the register in a plurality of processing cycles preceding the current processing cycle.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for simulating a concrete mixture. One of the methods includes obtaining an optical characterization of physical particles, generating a multispherical approximation of the physical particles, the multispherical approximation having reduced dimensionality compared to the optical characterization, simulating an aggregate mixture by applying the multispherical approximation of the particles to a physics simulator to obtain a predicted performance of the proposed aggregate mixture, selectively altering the aggregate mixture based on a comparison with performance metrics and simulating the altered aggregate mixture until the predicted performance satisfies the performance metrics to obtain a final aggregate mixture, and outputting the final aggregate mixture

A computer-implemented method of creating a design for a physical device using an inverse design process is provided. A computing system receives a proposed design. The computing system conducts an operational simulation based on the proposed design at a first resolution to generate a calculated performance result. The computing system provides the calculated performance result to a machine learning model to generate a predicted performance result of an operational simulation based on the proposed design at a second resolution, where the second resolution is higher than the first resolution. The computing system updates the proposed design based on the predicted performance result.

A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.

A method for generating a reliability performance model includes developing a reliability prediction machine learning model for predicting reliability performance of a product based on data obtained from manufacturing and testing of the product, and obtaining feature names for the reliability prediction machine learning model and their predictive power values. The feature names may correspond to features from the data obtained from manufacturing and testing of the product. The method may further include extracting a set of feature names corresponding to features having highest predictive power values from the feature names, and generating a reliability performance model using one or more model parameters derived from the set of feature names.

A process for scheduling engine inspection for a gas turbine engine includes computing an expected damage increment based on aircraft usage data of a single flight, computing a cumulative expected damage by summing the expected damage increment with a total set of historical expected damage increments since a previous maintenance, and determining an aggregate risk of failure based on the computed cumulative expected damage. A manual inspection is signaled when the aggregate risk of failure exceeds an acceptable risk threshold.