Disclosed is a condition assessment method for an outdoor post-mounted vacuum switch. The method includes: establishing a condition assessment mathematical model for the post-mounted vacuum switch and acquiring scores of condition indicators of the post-mounted vacuum switch; and acquiring a condition assessment score based on the condition assessment mathematical model of the post-mounted vacuum switch and according to the scores of the condition indicators of the post-mounted vacuum switch so as to realize on-line monitoring of a health condition of the post-mounted vacuum switch and assess the health condition of the post-mounted vacuum switch. Further disclosed is a condition assessment device for the outdoor post-mounted vacuum switch.

An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

A method and system for improving the performance of a computer in identifying and mitigating electromigration violations of a semiconductor device. A set of library gates is obtained and parasitic layout extraction is performed for each gate in the set of library gates to generate an extracted netlist. One or more passes of an electromigration analysis of the extracted netlist are performed to characterize each gate over a set of input parameters and to generate a maximum slew rate (MAX_SLEW) table and a maximum capacitance (MAX_CAP) table.

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and estimating a wire width associated with the electronic design based upon, at least in part, a current in a wire, a layer of the wire, a temperature, and an electromigration length. Embodiments may further include allowing, at a graphical user interface, a user to make an edit to a shape or a layer of the wire and generating a revised EM length, based upon, at least in part, the edit. Embodiments may also include generating one or more EM length breakpoints based upon, at least in part, the revised EM length and one or more EM rules.

A method and apparatus for determining the low-cycle fatigue of a mechanical component includes acquiring a plurality of cyclic operation conditions of a mechanical component in a plurality of operation cycles; for each of the plurality of operation cycles, calculating a Weibull proportional parameter on the basis of a corresponding cyclic operation condition from among the plurality of cyclic operation conditions; for each of the plurality of operation cycles, calculating the hazard rate of the mechanical component on the basis of the Weibull proportional parameter; and determining the low-cycle fatigue of the mechanical component on the basis of the hazard rate in the plurality of operation cycles, wherein the Weibull proportional parameter is used for describing the geometrical shape and the stress-strain state of the mechanical component.

A stretchable electronics generating apparatus and layout method thereof are provided. The layout method includes: establishing a layout database, wherein the layout database recodes a plurality of layout selection information respectively corresponding to a plurality of strain/stress information; detecting a layout target area to obtain a strain/stress distribution status of the layout target area; generating a wire routing information according to the strain/stress distribution status based on the layout database; and transporting the wire routing information to a manufacture device of the conductive wires for disposing a plurality of physical conductive wires on the layout target area by the manufacture device.

A method for aging simulation model establishment includes following operations. Provide a planar p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) having a source and a drain. Measure a first reliability degradation data of the pMOSFET. Select a model for the pMOSFET with modeling parameters related to hot carrier induced punch-through (HEIP). The modeling parameters comprise hot carrier injection (HCI) parameters used to fix a simulated current relation between the source and the drain. Construct the modeling parameters by aging parameters multiplied corresponding flags. Perform a simulation of the pMOSFET with the model to have a second reliability degradation data. Update the aging parameters and re-performing the simulation if the first reliability degradation data and second reliability degradation data are not matched. Collect the aging parameters when the first reliability degradation data and the second reliability degradation data are matched to establish the aging simulation model for the pMOSFET.

Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.